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On April 1st 2003 the following semiconductor operations were transferred to Renesas Technology Corporation: operations covering microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.). Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have all been changed to Renesas Technology Corporation. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Thank you for your understanding. Renesas Technology Home Page: www.renesas.com
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Renesas Technology Corp. April 1, 2003
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Hitachi 16-Bit Single-Chip Microcomputer
H8S/2615 Series
H8S/2615 HD64F2615 HD6432615 Hardware Manual Preliminary
ADE-602-309 Rev. 0.5 03/10/03 Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Rev. 0.5, 03/03, page ii of xxvi
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 0.5, 03/03, page iii of xxvi
Configuration of This Manual
This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules * * CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 0.5, 03/03, page iv of xxvi
Preface
The H8S/2615 Series are single-chip microcomputers made up of the high-speed H8S/2600 CPU as its core, and the peripheral functions required to configure a system. The H8S/2600 CPU has an instruction set that is compatible with the H8/300 and H8/300H CPUs. This LSI is equipped with ROM and RAM memory, a 16-bit timer pulse unit (TPU), a watchdog timer (WDT), a serial communication interface (SCI), a Hitachi controller area network (HCAN), an A/D converter, and I/O ports as on-chip peripheral modules required for system configuration. This LSI is suitable for use as an embedded microcomputer for high-level control systems. A single-power flash memory (F-ZTAT ) version is available for this LSI's ROM. This provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change.
TM
Note: * F-ZTAT
TM
is a trademark of Hitachi, Ltd.
Target Users: This manual was written for users who will be using the H8S/2615 Series in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2615 Series to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.
Rev. 0.5, 03/03, page v of xxvi
* In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 17, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right.
Bit order: Related Manuals:
The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/
H8S/2615 Series manuals:
Manual Title H8S/2615 Series Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE No. This manual ADE-602-083
User's manuals for development tools:
Manual Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging Interface Tutorial Hitachi Embedded Workshop User's Manual ADE No. ADE-702-247 ADE-702-282 ADE-702-231 ADE-702-201
Rev. 0.5, 03/03, page vi of xxvi
Contents
Section 1 Overview............................................................................................1
1.1 1.2 1.3 1.4 Features ............................................................................................................................. 1 Internal Block Diagram..................................................................................................... 2 Pin Arrangement ............................................................................................................... 3 Pin Functions .................................................................................................................... 4
Section 2 CPU....................................................................................................9
2.1 Features ............................................................................................................................. 9 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 10 2.1.2 Differences from H8/300 CPU ............................................................................ 11 2.1.3 Differences from H8/300H CPU.......................................................................... 11 CPU Operating Modes ...................................................................................................... 12 2.2.1 Normal Mode....................................................................................................... 12 2.2.2 Advanced Mode................................................................................................... 13 Address Space................................................................................................................... 16 Register Configuration...................................................................................................... 17 2.4.1 General Registers ................................................................................................. 18 2.4.2 Program Counter (PC) ......................................................................................... 19 2.4.3 Extended Control Register (EXR) ....................................................................... 19 2.4.4 Condition-Code Register (CCR) .......................................................................... 20 2.4.5 Multiply-Accumulate Register (MAC) ................................................................ 21 2.4.6 Initial Values of CPU Registers ........................................................................... 21 Data Formats..................................................................................................................... 22 2.5.1 General Register Data Formats ............................................................................ 22 2.5.2 Memory Data Formats ......................................................................................... 24 Instruction Set ................................................................................................................... 25 2.6.1 Table of Instructions Classified by Function ....................................................... 26 2.6.2 Basic Instruction Formats .................................................................................... 35 Addressing Modes and Effective Address Calculation ..................................................... 37 2.7.1 Register Direct--Rn............................................................................................. 37 2.7.2 Register Indirect--@ERn .................................................................................... 37 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn).............. 37 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn .. 38 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32.................................... 38 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 ................................................................. 39 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC).................................... 39 2.7.8 Memory Indirect--@@aa:8 ................................................................................ 39 2.7.9 Effective Address Calculation ............................................................................. 40 Processing States............................................................................................................... 43
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2.2
2.3 2.4
2.5
2.6
2.7
2.8
2.9
Usage Notes ...................................................................................................................... 44 2.9.1 Usage Notes on Bit Manipulation Instructions .................................................... 44
Section 3 MCU Operating Modes .....................................................................45
3.1 3.2 Operating Mode Selection ................................................................................................ 45 Register Descriptions ........................................................................................................ 46 3.2.1 Mode Control Register (MDCR) ......................................................................... 46 3.2.2 System Control Register (SYSCR) ...................................................................... 46 Pin Functions in Each Operating Mode ............................................................................ 48 3.3.1 Pin Functions ....................................................................................................... 48 Address Map ..................................................................................................................... 49
3.3 3.4
Section 4 Exception Handling ...........................................................................51
4.1 4.2 4.3 Exception Handling Types and Priority ............................................................................ 51 Exception Sources and Exception Vector Table ............................................................... 51 Reset ................................................................................................................................. 53 4.3.1 Reset Exception Handling.................................................................................... 53 4.3.2 Interrupts after Reset............................................................................................ 55 4.3.3 State of On-Chip Peripheral Modules after Reset Release................................... 55 Traces................................................................................................................................ 56 Interrupts ........................................................................................................................... 56 Trap Instruction................................................................................................................. 57 Stack Status after Exception Handling.............................................................................. 58 Usage Note........................................................................................................................ 59
4.4 4.5 4.6 4.7 4.8
Section 5 Interrupt Controller............................................................................61
5.1 5.2 5.3 Features ............................................................................................................................. 61 Input/Output Pins .............................................................................................................. 63 Register Descriptions ........................................................................................................ 63 5.3.1 Interrupt Priority Registers A, B, D to H, J, K, M (IPRA, IPRB, IPRD to IPRH, IPRJ, IPRK, IPRM) ............................................. 64 5.3.2 IRQ Enable Register (IER) .................................................................................. 65 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 66 5.3.4 IRQ Status Register (ISR).................................................................................... 68 Interrupt ............................................................................................................................ 68 5.4.1 External Interrupts ............................................................................................... 68 5.4.2 Internal Interrupts................................................................................................. 69 Interrupt Exception Handling Vector Table...................................................................... 69 Interrupt Control Modes and Interrupt Operation ............................................................. 72 5.6.1 Interrupt Control Mode 0 ..................................................................................... 72 5.6.2 Interrupt Control Mode 2 ..................................................................................... 74 5.6.3 Interrupt Exception Handling Sequence .............................................................. 75 5.6.4 Interrupt Response Times .................................................................................... 77
5.4
5.5 5.6
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5.7
Usage Notes ...................................................................................................................... 78 5.7.1 Contention between Interrupt Generation and Disabling..................................... 78 5.7.2 Instructions that Disable Interrupts ...................................................................... 79 5.7.3 When Interrupts are Disabled .............................................................................. 79 5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 80
Section 6 Bus Controller....................................................................................81
6.1 Basic Timing ..................................................................................................................... 81 6.1.1 On-Chip Memory Access Timing (ROM, RAM) ................................................ 81 6.1.2 On-Chip Peripheral Module Access Timing........................................................ 82 6.1.3 On-Chip HCAN Module Access Timing ............................................................. 83
Section 7 I/O Ports .............................................................................................85
7.1 Port 1................................................................................................................................. 88 7.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 88 7.1.2 Port 1 Data Register (P1DR)................................................................................ 88 7.1.3 Port 1 Register (PORT1)...................................................................................... 89 7.1.4 Pin Functions ....................................................................................................... 89 Port 4................................................................................................................................. 92 7.2.1 Port 4 Register (PORT4)...................................................................................... 92 Port 9................................................................................................................................. 92 7.3.1 Port 9 Register (PORT9)...................................................................................... 92 Port A................................................................................................................................ 93 7.4.1 Port A Data Direction Register (PADDR) ........................................................... 93 7.4.2 Port A Data Register (PADR) .............................................................................. 94 7.4.3 Port A Register (PORTA) .................................................................................... 94 7.4.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................ 95 7.4.5 Port A Open-Drain Control Register (PAODR) .................................................. 95 7.4.6 Pin Functions ....................................................................................................... 96 Port B ................................................................................................................................ 96 7.5.1 Port B Data Direction Register (PBDDR)............................................................ 97 7.5.2 Port B Data Register (PBDR) .............................................................................. 97 7.5.3 Port B Register (PORTB) .................................................................................... 98 7.5.4 Port B Pull-Up MOS Control Register (PBPCR)................................................. 98 7.5.5 Port B Open-Drain Control Register (PBODR) ................................................... 99 7.5.6 Pin Functions ....................................................................................................... 99 Port C ................................................................................................................................ 101 7.6.1 Port C Data Direction Register (PCDDR)............................................................ 101 7.6.2 Port C Data Register (PCDR) .............................................................................. 102 7.6.3 Port C Register (PORTC) .................................................................................... 103 7.6.4 Port C Pull-Up MOS Control Register (PCPCR)................................................. 103 7.6.5 Port C Open-Drain Control Register (PCODR) ................................................... 104 7.6.6 Pin Functions ....................................................................................................... 104
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7.2 7.3 7.4
7.5
7.6
7.7
7.8
Port D................................................................................................................................ 106 7.7.1 Port D Data Direction Register (PDDDR) ........................................................... 106 7.7.2 Port D Data Register (PDDR) .............................................................................. 107 7.7.3 Port D Register (PORTD) .................................................................................... 107 7.7.4 Port D Pull-up MOS Control Register (PDPCR) ................................................. 108 7.7.5 Pin Function......................................................................................................... 108 Port F................................................................................................................................. 108 7.8.1 Port F Data Direction Register (PFDDR) ............................................................ 108 7.8.2 Port F Data Register (PFDR) ............................................................................... 109 7.8.3 Port F Register (PORTF) ..................................................................................... 110 7.8.4 Pin Functions ....................................................................................................... 110
Section 8 16-Bit Timer Pulse Unit (TPU) .........................................................113
8.1 8.2 8.3 Features ............................................................................................................................. 113 Input/Output Pins .............................................................................................................. 117 Register Descriptions ........................................................................................................ 118 8.3.1 Timer Control Register (TCR) ............................................................................. 120 8.3.2 Timer Mode Register (TMDR) ............................................................................ 125 8.3.3 Timer I/O Control Register (TIOR) ..................................................................... 127 8.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 144 8.3.5 Timer Status Register (TSR)................................................................................ 145 8.3.6 Timer Counter (TCNT)........................................................................................ 148 8.3.7 Timer General Register (TGR) ............................................................................ 148 8.3.8 Timer Start Register (TSTR)................................................................................ 148 8.3.9 Timer Synchro Register (TSYR) ......................................................................... 149 Operation .......................................................................................................................... 150 8.4.1 Basic Functions.................................................................................................... 150 8.4.2 Synchronous Operation........................................................................................ 156 8.4.3 Buffer Operation .................................................................................................. 157 8.4.4 Cascaded Operation ............................................................................................. 161 8.4.5 PWM Modes ........................................................................................................ 162 8.4.6 Phase Counting Mode .......................................................................................... 167 Interrupts ........................................................................................................................... 173 A/D Converter Activation ................................................................................................. 175 Operation Timing.............................................................................................................. 176 8.7.1 Input/Output Timing ............................................................................................ 176 8.7.2 Interrupt Signal Timing........................................................................................ 180 Usage Notes ...................................................................................................................... 183 8.8.1 Module Stop Mode Setting .................................................................................. 183 8.8.2 Input Clock Restrictions ...................................................................................... 183 8.8.3 Caution on Period Setting .................................................................................... 184 8.8.4 Contention between TCNT Write and Clear Operations..................................... 184 8.8.5 Contention between TCNT Write and Increment Operations.............................. 185
8.4
8.5 8.6 8.7
8.8
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8.8.6 8.8.7 8.8.8 8.8.9 8.8.10 8.8.11 8.8.12 8.8.13 8.8.14
Contention between TGR Write and Compare Match ......................................... 185 Contention between Buffer Register Write and Compare Match ........................ 186 Contention between TGR Read and Input Capture.............................................. 187 Contention between TGR Write and Input Capture............................................. 187 Contention between Buffer Register Write and Input Capture ............................ 188 Contention between Overflow/Underflow and Counter Clearing........................ 189 Contention between TCNT Write and Overflow/Underflow............................... 190 Multiplexing of I/O Pins ...................................................................................... 190 Interrupts in Module Stop Mode.......................................................................... 190
Section 9 Watchdog Timer (WDT)....................................................................191
9.1 9.2 Features ............................................................................................................................. 191 Register Descriptions ........................................................................................................ 193 9.2.1 Timer Counter (TCNT)........................................................................................ 193 9.2.2 Timer Control/Status Register (TCSR) ................................................................ 193 9.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 197 Operation .......................................................................................................................... 198 9.3.1 Watchdog Timer Mode ........................................................................................ 198 9.3.2 Interval Timer Mode ............................................................................................ 200 Interrupt Sources............................................................................................................... 200 Usage Notes ...................................................................................................................... 200 9.5.1 Notes on Register Access..................................................................................... 200 9.5.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 201 9.5.3 Changing Value of CKS2 to CKS0...................................................................... 202 9.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 202 9.5.5 Internal Reset in Watchdog Timer Mode............................................................. 202 9.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 202
9.3
9.4 9.5
Section 10 Serial Communication Interface (SCI) ............................................203
10.1 Features ............................................................................................................................. 203 10.2 Input/Output Pins .............................................................................................................. 205 10.3 Register Descriptions ........................................................................................................ 205 10.3.1 Receive Shift Register (RSR) .............................................................................. 206 10.3.2 Receive Data Register (RDR) .............................................................................. 206 10.3.3 Transmit Data Register (TDR)............................................................................. 206 10.3.4 Transmit Shift Register (TSR) ............................................................................. 206 10.3.5 Serial Mode Register (SMR)................................................................................ 207 10.3.6 Serial Control Register (SCR).............................................................................. 210 10.3.7 Serial Status Register (SSR) ................................................................................ 212 10.3.8 Smart Card Mode Register (SCMR) .................................................................... 217 10.3.9 Bit Rate Register (BRR) ...................................................................................... 218 10.4 Operation in Asynchronous Mode .................................................................................... 225 10.4.1 Data Transfer Format........................................................................................... 225
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10.5
10.6
10.7
10.8
10.9
10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 227 10.4.3 Clock.................................................................................................................... 228 10.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 229 10.4.5 Data Transmission (Asynchronous Mode)........................................................... 230 10.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 232 Multiprocessor Communication Function......................................................................... 236 10.5.1 Multiprocessor Serial Data Transmission ............................................................ 238 10.5.2 Multiprocessor Serial Data Reception ................................................................. 239 Operation in Clocked Synchronous Mode ........................................................................ 242 10.6.1 Clock.................................................................................................................... 242 10.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 243 10.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 244 10.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 247 10.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 249 Operation in Smart Card Interface .................................................................................... 251 10.7.1 Pin Connection Example...................................................................................... 251 10.7.2 Data Format (Except for Block Transfer Mode).................................................. 252 10.7.3 Block Transfer Mode ........................................................................................... 253 10.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode.............................................................................. 254 10.7.5 Initialization ......................................................................................................... 255 10.7.6 Data Transmission (Except for Block Transfer Mode) ........................................ 255 10.7.7 Serial Data Reception (Except for Block Transfer Mode) ................................... 258 10.7.8 Clock Output Control........................................................................................... 259 Interrupt Sources............................................................................................................... 261 10.8.1 Interrupts in Normal Serial Communication Interface Mode .............................. 261 10.8.2 Interrupts in Smart Card Interface Mode ............................................................. 262 Usage Notes ...................................................................................................................... 263 10.9.1 Module Stop Mode Setting .................................................................................. 263 10.9.2 Break Detection and Processing .......................................................................... 263 10.9.3 Mark State and Break Detection .......................................................................... 263 10.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) .................................................................... 263
Section 11 Hitachi Controller Area Network (HCAN) .....................................265
11.1 Features ............................................................................................................................. 265 11.2 Input/Output Pins .............................................................................................................. 267 11.3 Register Descriptions ........................................................................................................ 267 11.3.1 Master Control Register (MCR)........................................................................... 268 11.3.2 General Status Register (GSR) ............................................................................ 269 11.3.3 Bit Configuration Register (BCR) ....................................................................... 271 11.3.4 Mailbox Configuration Register (MBCR) ........................................................... 273
Rev. 0.5, 03/03, page xii of xxvi
11.4
11.5 11.6 11.7
11.3.5 Transmit Wait Register (TXPR) .......................................................................... 274 11.3.6 Transmit Wait Cancel Register (TXCR).............................................................. 275 11.3.7 Transmit Acknowledge Register (TXACK) ........................................................ 276 11.3.8 Abort Acknowledge Register (ABACK) ............................................................. 277 11.3.9 Receive Complete Register (RXPR) .................................................................... 278 11.3.10 Remote Request Register (RFPR)........................................................................ 279 11.3.11 Interrupt Register (IRR) ....................................................................................... 280 11.3.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 283 11.3.13 Interrupt Mask Register (IMR) ............................................................................ 284 11.3.14 Receive Error Counter (REC) .............................................................................. 285 11.3.15 Transmit Error Counter (TEC)............................................................................. 285 11.3.16 Unread Message Status Register (UMSR) ........................................................... 286 11.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 287 11.3.18 Message Control (MC0 to MC15) ....................................................................... 289 11.3.19 Message Data (MD0 to MD15) ........................................................................... 291 11.3.20 HCAN Monitor Register (HCANMON).............................................................. 291 Operation .......................................................................................................................... 293 11.4.1 Hardware and Software Resets ............................................................................ 293 11.4.2 Initialization after Hardware Reset ...................................................................... 293 11.4.3 Message Transmission ......................................................................................... 299 11.4.4 Message Reception .............................................................................................. 302 11.4.5 HCAN Sleep Mode .............................................................................................. 305 11.4.6 HCAN Halt Mode ................................................................................................ 306 Interrupt Sources............................................................................................................... 307 CAN Bus Interface............................................................................................................ 308 Usage Notes ...................................................................................................................... 308 11.7.1 Module Stop Mode Setting .................................................................................. 308 11.7.2 Reset..................................................................................................................... 308 11.7.3 HCAN Sleep Mode .............................................................................................. 309 11.7.4 Interrupts.............................................................................................................. 309 11.7.5 Error Counters...................................................................................................... 309 11.7.6 Register Access.................................................................................................... 309 11.7.7 HCAN Medium-Speed Mode .............................................................................. 309 11.7.8 Register Hold in Standby Modes ......................................................................... 309 11.7.9 Use on Bit Manipulation Instructions .................................................................. 309 11.7.10 HCAN TXCR Operation...................................................................................... 310
Section 12 A/D Converter..................................................................................311
12.1 Features ............................................................................................................................. 311 12.2 Input/Output Pins .............................................................................................................. 313 12.3 Register Descriptions ........................................................................................................ 314 12.3.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 314 12.3.2 A/D Control/Status Register (ADCSR) ............................................................... 315
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12.3.3 A/D Control Register (ADCR) ............................................................................ 317 12.4 Operation .......................................................................................................................... 318 12.4.1 Single Mode......................................................................................................... 318 12.4.2 Scan Mode ........................................................................................................... 318 12.4.3 Input Sampling and A/D Conversion Time ......................................................... 319 12.4.4 External Trigger Input Timing............................................................................. 321 12.5 Interrupt Sources............................................................................................................... 321 12.6 A/D Conversion Accuracy Definitions ............................................................................. 322 12.7 Usage Notes ...................................................................................................................... 324 12.7.1 Module Stop Mode Setting .................................................................................. 324 12.7.2 Permissible Signal Source Impedance ................................................................. 324 12.7.3 Influences on Absolute Accuracy ........................................................................ 324 12.7.4 Range of Analog Power Supply and Other Pin Settings ...................................... 325 12.7.5 Notes on Board Design ........................................................................................ 325 12.7.6 Notes on Noise Countermeasures ........................................................................ 325
Section 13 RAM ................................................................................................327 Section 14 ROM ................................................................................................329
14.1 14.2 14.3 14.4 14.5 Features ............................................................................................................................. 329 Mode Transitions .............................................................................................................. 330 Block Configuration.......................................................................................................... 334 Input/Output Pins .............................................................................................................. 335 Register Descriptions ........................................................................................................ 335 14.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 336 14.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 337 14.5.3 Erase Block Register 1 (EBR1) ........................................................................... 337 14.5.4 RAM Emulation Register (RAMER)................................................................... 338 14.5.5 Flash Memory Power Control Register (FLPWCR) ............................................ 339 On-Board Programming Modes........................................................................................ 339 14.6.1 Boot Mode ........................................................................................................... 340 14.6.2 Programming/Erasing in User Program Mode..................................................... 342 Flash Memory Emulation in RAM ................................................................................... 343 Flash Memory Programming/Erasing ............................................................................... 345 14.8.1 Program/Program-Verify ..................................................................................... 345 14.8.2 Erase/Erase-Verify............................................................................................... 347 14.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 347 Program/Erase Protection ................................................................................................. 349 14.9.1 Hardware Protection ............................................................................................ 349 14.9.2 Software Protection.............................................................................................. 349 14.9.3 Error Protection.................................................................................................... 349 Programmer Mode ............................................................................................................ 350 Power-Down States for Flash Memory............................................................................. 350
14.6
14.7 14.8
14.9
14.10 14.11
Rev. 0.5, 03/03, page xiv of xxvi
Section 15 Clock Pulse Generator .....................................................................351
15.1 Register Descriptions ........................................................................................................ 352 15.1.1 System Clock Control Register (SCKCR) ........................................................... 352 15.1.2 Low-Power Control Register (LPWRCR) ........................................................... 353 15.2 Oscillator........................................................................................................................... 354 15.2.1 Connecting a Crystal Resonator........................................................................... 354 15.2.2 External Clock Input ............................................................................................ 355 15.3 PLL Circuit ....................................................................................................................... 357 15.4 Subclock Divider .............................................................................................................. 357 15.5 Medium-Speed Clock Divider .......................................................................................... 357 15.6 Bus Master Clock Selection Circuit .................................................................................. 357 15.7 Usage Notes ...................................................................................................................... 358 15.7.1 Note on Crystal Resonator ................................................................................... 358 15.7.2 Note on Board Design.......................................................................................... 358
Section 16 Power-Down Modes ........................................................................361
16.1 Register Descriptions ........................................................................................................ 365 16.1.1 Standby Control Register (SBYCR) .................................................................... 365 16.1.2 Low-Power Control Register (LPWRCR) ........................................................... 367 16.1.3 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)................... 368 16.2 Medium-Speed Mode........................................................................................................ 370 16.3 Sleep Mode ....................................................................................................................... 371 16.3.1 Transition to Sleep Mode..................................................................................... 371 16.3.2 Clearing Sleep Mode............................................................................................ 371 16.4 Software Standby Mode.................................................................................................... 372 16.4.1 Transition to Software Standby Mode ................................................................. 372 16.4.2 Clearing Software Standby Mode ........................................................................ 372 16.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 373 16.4.4 Software Standby Mode Application Example.................................................... 373 16.5 Hardware Standby Mode .................................................................................................. 374 16.5.1 Transition to Hardware Standby Mode ................................................................ 374 16.5.2 Clearing Hardware Standby Mode....................................................................... 375 16.5.3 Hardware Standby Mode Timings ....................................................................... 375 16.6 Module Stop Mode ........................................................................................................... 376 16.7 Watch Mode...................................................................................................................... 376 16.7.1 Transition to Watch Mode ................................................................................... 376 16.7.2 Canceling Watch Mode........................................................................................ 376 16.8 Subsleep Mode.................................................................................................................. 377 16.8.1 Transition to Subsleep Mode ............................................................................... 377 16.8.2 Canceling Subsleep Mode.................................................................................... 377 16.9 Subactive Mode ................................................................................................................ 378 16.9.1 Transition to Subactive Mode .............................................................................. 378 16.9.2 Canceling Subactive Mode .................................................................................. 378
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16.10 Direct Transitions.............................................................................................................. 378 16.10.1 Direct Transitions from High-Speed Mode to Subactive Mode........................... 379 16.10.2 Direct Transitions from Subactive Mode to High-Speed Mode........................... 379 16.11 Clock Output Disabling Function .................................................................................. 379 16.12 Usage Notes ...................................................................................................................... 380 16.12.1 I/O Port Status...................................................................................................... 380 16.12.2 Current Consumption during Oscillation Stabilization Wait Period .................... 380 16.12.3 On-Chip Peripheral Module Interrupt.................................................................. 380 16.12.4 Writing to MSTPCR ............................................................................................ 380
Section 17 List of Registers...............................................................................381
17.1 Register Addresses (Address Order) ................................................................................. 382 17.2 Register Bits...................................................................................................................... 395 17.3 Register States in Each Operating Mode........................................................................... 407
Section 18 Electrical Characteristics .................................................................417
18.1 Absolute Maximum Ratings ............................................................................................. 417 18.2 DC Characteristics ............................................................................................................ 418 18.3 AC Characteristics ............................................................................................................ 420 18.3.1 Clock Timing ....................................................................................................... 421 18.3.2 Control Signal Timing ......................................................................................... 422 18.3.3 Timing of On-Chip Peripheral Modules .............................................................. 424 18.4 A/D Conversion Characteristics........................................................................................ 427 18.5 Flash Memory Characteristics........................................................................................... 428
Appendix
A. B. C.
.........................................................................................................431
I/O Port States in Each Pin State....................................................................................... 431 Product Code Lineup ........................................................................................................ 432 Package Dimensions ......................................................................................................... 433
Index
.........................................................................................................435
Rev. 0.5, 03/03, page xvi of xxvi
Figures
Section 1 Overview Figure 1.1 Internal Block Diagram .................................................................................................2 Figure 1.2 Pin Arrangement............................................................................................................3 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) .....................................................................13 Figure 2.2 Stack Structure in Normal Mode .................................................................................13 Figure 2.3 Exception Vector Table (Advanced Mode) .................................................................14 Figure 2.4 Stack Structure in Advanced Mode .............................................................................15 Figure 2.5 Memory Map ...............................................................................................................16 Figure 2.6 CPU Registers .............................................................................................................17 Figure 2.7 Usage of General Registers .........................................................................................18 Figure 2.8 Stack ............................................................................................................................19 Figure 2.9 General Register Data Formats (1) ..............................................................................22 Figure 2.9 General Register Data Formats (2) ..............................................................................23 Figure 2.10 Memory Data Formats...............................................................................................24 Figure 2.11 Instruction Formats (Examples) ................................................................................36 Figure 2.12 Branch Address Specification in Memory Indirect Mode .........................................40 Figure 2.13 State Transitions ........................................................................................................44 Section 3 MCU Operating Modes Figure 3.1 Address Map................................................................................................................49 Section 4 Exception Handling Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)................................54 Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled: Cannot be Used in this LSI) .........................................................................................55 Figure 4.3 Stack Status after Exception Handling ........................................................................58 Figure 4.4 Operation when SP Value is Odd ................................................................................59 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Interrupt Controller Block Diagram of Interrupt Controller ........................................................................62 Block Diagram of Interrupts IRQ0 to IRQ5 ................................................................69 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0......73 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2.....................75 Interrupt Exception Handling ......................................................................................76 Contention between Interrupt Generation and Disabling ............................................79 Bus Controller On-Chip Memory Access Cycle..................................................................................81 On-Chip Support Module Access Cycle......................................................................82 On-Chip HCAN Module Access Cycle (Wait States Inserted) ...................................83
Rev. 0.5, 03/03, page xvii of xxvi
Section 8 16-Bit Timer Pulse Unit (TPU) Figure 8.1 Block Diagram of TPU.............................................................................................. 116 Figure 8.2 Example of Counter Operation Setting Procedure .................................................... 150 Figure 8.3 Free-Running Counter Operation .............................................................................. 151 Figure 8.4 Periodic Counter Operation....................................................................................... 152 Figure 8.5 Example of Setting Procedure for Waveform Output by Compare Match................ 152 Figure 8.6 Example of 0 Output/1 Output Operation ................................................................. 153 Figure 8.7 Example of Toggle Output Operation ....................................................................... 153 Figure 8.8 Example of Input Capture Operation Setting Procedure ........................................... 154 Figure 8.9 Example of Input Capture Operation......................................................................... 155 Figure 8.10 Example of Synchronous Operation Setting Procedure .......................................... 156 Figure 8.11 Example of Synchronous Operation........................................................................ 157 Figure 8.12 Compare Match Buffer Operation........................................................................... 158 Figure 8.13 Input Capture Buffer Operation............................................................................... 158 Figure 8.14 Example of Buffer Operation Setting Procedure..................................................... 159 Figure 8.15 Example of Buffer Operation (1)............................................................................. 160 Figure 8.16 Example of Buffer Operation (2)............................................................................. 160 Figure 8.17 Cascaded Operation Setting Procedure ................................................................... 161 Figure 8.18 Example of Cascaded Operation (1)........................................................................ 162 Figure 8.19 Example of Cascaded Operation (2)........................................................................ 162 Figure 8.20 Example of PWM Mode Setting Procedure ............................................................ 164 Figure 8.21 Example of PWM Mode Operation (1) ................................................................... 164 Figure 8.22 Example of PWM Mode Operation (2) ................................................................... 165 Figure 8.23 Example of PWM Mode Operation (3) ................................................................... 166 Figure 8.24 Example of Phase Counting Mode Setting Procedure............................................. 167 Figure 8.25 Example of Phase Counting Mode 1 Operation ...................................................... 168 Figure 8.26 Example of Phase Counting Mode 2 Operation ...................................................... 169 Figure 8.27 Example of Phase Counting Mode 3 Operation ...................................................... 170 Figure 8.28 Example of Phase Counting Mode 4 Operation ...................................................... 171 Figure 8.29 Phase Counting Mode Application Example........................................................... 173 Figure 8.30 Count Timing in Internal Clock Operation.............................................................. 176 Figure 8.31 Count Timing in External Clock Operation............................................................. 176 Figure 8.32 Output Compare Output Timing.............................................................................. 177 Figure 8.33 Input Capture Input Signal Timing.......................................................................... 177 Figure 8.34 Counter Clear Timing (Compare Match) ................................................................ 178 Figure 8.35 Counter Clear Timing (Input Capture) .................................................................... 178 Figure 8.36 Buffer Operation Timing (Compare Match)............................................................ 179 Figure 8.37 Buffer Operation Timing (Input Capture) ............................................................... 179 Figure 8.38 TGI Interrupt Timing (Compare Match) ................................................................. 180 Figure 8.39 TGI Interrupt Timing (Input Capture) ..................................................................... 180 Figure 8.40 TCIV Interrupt Setting Timing................................................................................ 181 Figure 8.41 TCIU Interrupt Setting Timing................................................................................ 181 Figure 8.42 Timing for Status Flag Clearing by CPU ................................................................ 182
Rev. 0.5, 03/03, page xviii of xxvi
Figure 8.43 Figure 8.44 Figure 8.45 Figure 8.46 Figure 8.47 Figure 8.48 Figure 8.49 Figure 8.50 Figure 8.51 Figure 8.52
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ..................183 Contention between TCNT Write and Clear Operations .........................................184 Contention between TCNT Write and Increment Operations .................................185 Contention between TGR Write and Compare Match.............................................186 Contention between Buffer Register Write and Compare Match ............................186 Contention between TGR Read and Input Capture .................................................187 Contention between TGR Write and Input Capture ................................................188 Contention between Buffer Register Write and Input Capture................................188 Contention between Overflow and Counter Clearing..............................................189 Contention between TCNT Write and Overflow.....................................................190
Section 9 Watchdog Timer (WDT) Figure 9.1 Block Diagram of WDT_0 ........................................................................................192 Figure 9.2 Block Diagram of WDT_1 ........................................................................................192 Figure 9.3 (a) WDT_0 Operation in Watchdog Timer Mode .....................................................199 Figure 9.3 (b) WDT_1 Operation in Watchdog Timer Mode .....................................................199 Figure 9.4 Writing to TCNT, TCSR, and RSTCSR (example for WDT0) .................................201 Figure 9.5 Contention between TCNT Write and Increment......................................................201 Section 10 Serial Communication Interface (SCI) Figure 10.1 Block Diagram of SCI .............................................................................................204 Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ..................................................225 Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode ........................................227 Figure 10.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) .............................................................................................228 Figure 10.5 Sample SCI Initialization Flowchart .......................................................................229 Figure 10.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit).....................................................230 Figure 10.7 Sample Serial Transmission Flowchart ...................................................................231 Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit).....................................................232 Figure 10.9 Sample Serial Reception Data Flowchart (1) ..........................................................234 Figure 10.9 Sample Serial Reception Data Flowchart (2) ..........................................................235 Figure 10.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ...........................................237 Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart ........................................238 Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ..............................239 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1) ........................................240 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2) ........................................241 Figure 10.14 Data Format in Synchronous Communication (For LSB-First).............................242 Figure 10.15 Sample SCI Initialization Flowchart......................................................................243 Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ..................245
Rev. 0.5, 03/03, page xix of xxvi
Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26 Figure 10.27 Figure 10.28 Figure 10.29 Figure 10.30 Figure 10.31 Figure 10.32
Sample Serial Transmission Flowchart ................................................................. 246 Example of SCI Operation in Reception ............................................................... 247 Sample Serial Reception Flowchart....................................................................... 248 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ...... 250 Schematic Diagram of Smart Card Interface Pin Connections.............................. 251 Normal Smart Card Interface Data Format............................................................ 252 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 252 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 253 Receive Data Sampling Timing in Smart Card Interface Mode (Using Clock of 372 Times the Transfer Rate) ...................................................... 254 Retransfer Operation in SCI Transmit Mode......................................................... 256 TEND Flag Generation Timing in Transmission Operation.................................. 256 Example of Transmission Processing Flow........................................................... 257 Retransfer Operation in SCI Receive Mode .......................................................... 258 Example of Reception Processing Flow ................................................................ 259 Timing for Fixing Clock Output Level.................................................................. 259 Clock Halt and Restart Procedure ......................................................................... 260
Section 11 Hitachi Controller Area Network (HCAN) Figure 11.1 HCAN Block Diagram ............................................................................................ 266 Figure 11.2 Message Control Register Configuration ................................................................ 289 Figure 11.3 Standard Format ...................................................................................................... 289 Figure 11.4 Extended Format ..................................................................................................... 289 Figure 11.5 Message Data Configuration ................................................................................... 291 Figure 11.6 Hardware Reset Flowchart ...................................................................................... 294 Figure 11.7 Software Reset Flowchart........................................................................................ 295 Figure 11.8 Detailed Description of One Bit .............................................................................. 296 Figure 11.9 Transmission Flowchart .......................................................................................... 299 Figure 11.10 Transmit Message Cancellation Flowchart ........................................................... 301 Figure 11.11 Reception Flowchart.............................................................................................. 302 Figure 11.12 Unread Message Overwrite Flowchart .................................................................. 304 Figure 11.13 HCAN Sleep Mode Flowchart .............................................................................. 305 Figure 11.14 HCAN Halt Mode Flowchart ................................................................................ 306 Figure 11.15 High-Speed Interface Using PCA82C250 ............................................................. 308 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 A/D Converter Block Diagram of A/D Converter ........................................................................... 312 A/D Conversion Timing .......................................................................................... 319 External Trigger Input Timing ................................................................................ 321 A/D Conversion Accuracy Definitions.................................................................... 323 A/D Conversion Accuracy Definitions.................................................................... 323 Example of Analog Input Circuit ............................................................................ 324 Example of Analog Input Protection Circuit ........................................................... 326 Analog Input Pin Equivalent Circuit ....................................................................... 326
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Section 14 ROM Figure 14.1 Block Diagram of Flash Memory ...........................................................................330 Figure 14.2 Flash Memory State Transitions..............................................................................331 Figure 14.3 Boot Mode...............................................................................................................332 Figure 14.4 User Program Mode ................................................................................................333 Figure 14.5 Flash Memory Block Configuration........................................................................334 Figure 14.6 Programming/Erasing Flowchart Example in User Program Mode ........................342 Figure 14.7 Flowchart for Flash Memory Emulation in RAM ...................................................343 Figure 14.8 Example of RAM Overlap Operation......................................................................344 Figure 14.9 Program/Program-Verify Flowchart........................................................................346 Figure 14.10 Erase/Erase-Verify Flowchart ...............................................................................348 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Clock Pulse Generator Block Diagram of Clock Pulse Generator ...............................................................351 Connection of Crystal Resonator (Example) ...........................................................354 Crystal Resonator Equivalent Circuit ......................................................................355 External Clock Input (Examples) ............................................................................355 External Clock Input Timing ...................................................................................356 Note on Board Design of Oscillator Circuit ............................................................358 External Circuitry Recommended for PLL Circuit..................................................359 Power-Down Modes Mode Transition Diagram........................................................................................362 Medium-Speed Mode Transition and Clearance Timing.........................................371 Software Standby Mode Application Example........................................................374 Timing of Transition to Hardware Standby Mode...................................................375 Timing of Recovery from Hardware Standby Mode ...............................................375
Section 18 Electrical Characteristics Figure 18.1 Output Load Circuit.................................................................................................420 Figure 18.2 System Clock Timing ..............................................................................................421 Figure 18.3 Oscillation Stabilization Timing..............................................................................422 Figure 18.4 Reset Input Timing ..................................................................................................423 Figure 18.5 Interrupt Input Timing .............................................................................................423 Figure 18.6 I/O Port Input/Output Timing..................................................................................425 Figure 18.7 TPU Input/Output Timing .......................................................................................425 Figure 18.8 TPU Clock Input Timing.........................................................................................426 Figure 18.9 SCK Clock Input Timing.........................................................................................426 Figure 18.10 SCI Input/Output Timing (Clocked Synchronous Mode)......................................426 Figure 18.11 A/D Converter External Trigger Input Timing......................................................426 Figure 18.12 HCAN Input/Output Timing..................................................................................427 Appendix Figure C.1 FP-80Q Package Dimensions ...................................................................................433
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Tables
Section 2 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 CPU Instruction Classification ............................................................................................25 Operation Notation......................................................................................................26 Data Transfer Instructions...........................................................................................27 Arithmetic Operations Instructions (1) .......................................................................28 Arithmetic Operations Instructions (2) .......................................................................29 Logic Operations Instructions .....................................................................................30 Shift Instructions.........................................................................................................30 Bit Manipulation Instructions (1)................................................................................31 Bit Manipulation Instructions (2)................................................................................32 Branch Instructions .....................................................................................................33 System Control Instructions........................................................................................34 Block Data Transfer Instructions ............................................................................35 Addressing Modes ..................................................................................................37 Absolute Address Access Ranges ...........................................................................38
Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection ................................................................................45 Table 3.2 Pin Functions in Each Operating Mode ......................................................................48 Section 4 Exception Handling Table 4.1 Exception Types and Priority......................................................................................51 Table 4.2 Exception Handling Vector Table...............................................................................52 Table 4.3 Status of CCR and EXR after Trace Exception Handling...........................................56 Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling ..........................57 Section 5 Interrupt Controller Table 5.1 Pin Configuration........................................................................................................63 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities.....................................70 Table 5.3 Interrupt Control Modes..............................................................................................72 Table 5.4 Interrupt Response Times ...........................................................................................77 Table 5.5 Number of States in Interrupt Handling Routine Execution Status.............................78 Section 7 I/O Ports Table 7.1 Port Functions .............................................................................................................86 Table 7.2 P17 Pin Function.........................................................................................................89 Table 7.3 P16 Pin Function.........................................................................................................90 Table 7.4 P15 Pin Function.........................................................................................................90 Table 7.5 P14 Pin Function.........................................................................................................90 Table 7.6 P13 Pin Function.........................................................................................................91 Table 7.7 P12 Pin Function.........................................................................................................91 Table 7.8 P11 Pin Function.........................................................................................................91
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Table 7.9 P10 Pin Function......................................................................................................... 91 Table 7.10 PA3 Pin Function.................................................................................................... 96 Table 7.11 PA2 Pin Function.................................................................................................... 96 Table 7.12 PA1 Pin Function.................................................................................................... 96 Table 7.13 PA0 Pin Function.................................................................................................... 96 Table 7.14 PB7 Pin Function .................................................................................................... 99 Table 7.15 PB6 Pin Function .................................................................................................... 99 Table 7.16 PB5 Pin Function .................................................................................................. 100 Table 7.17 PB4 Pin Function .................................................................................................. 100 Table 7.18 PB3 Pin Function .................................................................................................. 100 Table 7.19 PB2 Pin Function .................................................................................................. 100 Table 7.20 PB1 Pin Function .................................................................................................. 101 Table 7.21 PB0 Pin Function .................................................................................................. 101 Table 7.22 PC7 Pin Function .................................................................................................. 104 Table 7.23 PC6 Pin Function .................................................................................................. 104 Table 7.24 PC5 Pin Function .................................................................................................. 104 Table 7.25 PC4 Pin Function .................................................................................................. 105 Table 7.26 PC3 Pin Function .................................................................................................. 105 Table 7.27 PC2 Pin Function .................................................................................................. 105 Table 7.28 PC1 Pin Function .................................................................................................. 105 Table 7.29 PC0 Pin Function .................................................................................................. 105 Table 7.30 PDn Pin Function.................................................................................................. 108 Table 7.31 PF7 Pin Function .................................................................................................. 110 Table 7.32 PF6 Pin Function .................................................................................................. 110 Table 7.33 PF5 Pin Function .................................................................................................. 110 Table 7.34 PF4 Pin Function .................................................................................................. 111 Table 7.35 PF3 Pin Function .................................................................................................. 111 Table 7.36 PF2 Pin Function .................................................................................................. 111 Table 7.37 PF1 Pin Function .................................................................................................. 111 Table 7.38 PF0 Pin Function .................................................................................................. 111 Section 8 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Table 8.8 Table 8.9 Table 8.10 Table 8.11 16-Bit Timer Pulse Unit (TPU) TPU Functions .......................................................................................................... 114 Pin Configuration...................................................................................................... 117 CCLR0 to CCLR2 (channels 0 and 3) ...................................................................... 121 CCLR0 to CCLR2 (channels 1, 2, 4, and 5) ............................................................. 121 TPSC0 to TPSC2 (channel 0) ................................................................................... 122 TPSC0 to TPSC2 (channel 1) ................................................................................... 122 TPSC0 to TPSC2 (channels 2).................................................................................. 123 TPSC0 to TPSC2 (channel 3) ................................................................................... 123 TPSC0 to TPSC2 (channel 4) ................................................................................... 124 TPSC0 to TPSC2 (channel 5) ............................................................................... 124 MD0 to MD3 ........................................................................................................ 126
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Table 8.12 Table 8.13 Table 8.14 Table 8.15 Table 8.16 Table 8.17 Table 8.18 Table 8.19 Table 8.20 Table 8.21 Table 8.22 Table 8.23 Table 8.24 Table 8.25 Table 8.26 Table 8.27 Table 8.28 Table 8.29 Table 8.30 Table 8.31 Table 8.32 Table 8.33 Table 8.34 Table 8.35 Table 8.36
TIORH_0 (Channel 0) ..........................................................................................128 TIORL_0 (channel 0)............................................................................................129 TIOR_1 (Channel 1) .............................................................................................130 TIOR_2 (Channel 2) .............................................................................................131 TIORH_3 (Channel 3) ..........................................................................................132 TIORL_3 (Channel 3)...........................................................................................133 TIOR_4 (Channel 4) .............................................................................................134 TIOR_5 (Channel 5) .............................................................................................135 TIORH_0 (Channel 0) ..........................................................................................136 TIORL_0 (Channel 0)...........................................................................................137 TIOR_1 (Channel 1) .............................................................................................138 TIOR_2 (Channel 2) .............................................................................................139 TIORH_3 (Channel 3) ..........................................................................................140 TIORL_3 (Channel 3)...........................................................................................141 TIOR_4 (Channel 4) .............................................................................................142 TIOR_5 (Channel 5) .............................................................................................143 Register Combinations in Buffer Operation..........................................................158 Cascaded Combinations........................................................................................161 PWM Output Registers and Output Pins...............................................................163 Phase Counting Mode Clock Input Pins ...............................................................167 Up/Down-Count Conditions in Phase Counting Mode 1 ......................................168 Up/Down-Count Conditions in Phase Counting Mode 2 ......................................169 Up/Down-Count Conditions in Phase Counting Mode 3 ......................................170 Up/Down-Count Conditions in Phase Counting Mode 4 ......................................171 TPU Interrupts ......................................................................................................174
Section 9 Watchdog Timer (WDT) Table 9.1 WDT Interrupt Sources.............................................................................................200 Section 10 Serial Communication Interface (SCI) Table 10.1 Pin Configuration..................................................................................................205 Table 10.2 Relationships between N Setting in BRR and Bit Rate B .....................................218 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...........................219 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...........................220 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...........................221 Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)...........................221 Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................222 Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) .....................223 Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode).....223 Table 10.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372) .....................................................................................224 Table 10.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372)......................................................................................................224 Table 10.10 Serial Transfer Formats (Asynchronous Mode)....................................................226 Table 10.11 SSR Status Flags and Receive Data Handling ......................................................233
Rev. 0.5, 03/03, page xxv of xxvi
Table 10.12 Table 10.13
SCI Interrupt Sources............................................................................................ 261 SCI Interrupt Sources............................................................................................ 262
Section 11 Hitachi Controller Area Network (HCAN) Table 11.1 Pin Configuration.................................................................................................. 267 Table 11.2 Limits for Settable Value ...................................................................................... 296 Table 11.3 Setting Range for TSEG1 and TSEG2 in BCR..................................................... 297 Table 11.4 HCAN Interrupt Sources....................................................................................... 308 Section 12 A/D Converter Table 12.1 Pin Configuration.................................................................................................. 313 Table 12.2 Analog Input Channels and Corresponding ADDR Registers .............................. 314 Table 12.3 A/D Conversion Time (Single Mode)................................................................... 320 Table 12.4 A/D Conversion Time (Scan Mode) ..................................................................... 320 Table 12.5 A/D Converter Interrupt Source............................................................................ 321 Table 12.6 Analog Pin Specifications..................................................................................... 326 Section 14 ROM Table 14.1 Differences between Boot Mode and User Program Mode .................................. 331 Table 14.2 Pin Configuration.................................................................................................. 335 Table 14.3 Setting On-Board Programming Modes................................................................ 339 Table 14.4 Boot Mode Operation ........................................................................................... 341 Table 14.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible .................................................................................... 341 Table 14.6 Flash Memory Operating States............................................................................ 350 Section 15 Clock Pulse Generator Table 15.1 Damping Resistance Value ................................................................................... 354 Table 15.2 Crystal Resonator Characteristics ......................................................................... 355 Table 15.3 External Clock Input Conditions........................................................................... 356 Section 16 Power-Down Modes Table 16.1 Power-Down Mode Transition Conditions ........................................................... 363 Table 16.2 LSI Internal States in Each Mode ......................................................................... 364 Table 16.3 Oscillation Stabilization Time Settings................................................................. 373 Table 16.4 Pin State in Each Processing State..................................................................... 389 Section 18 Electrical Characteristics Table 18.1 Absolute Maximum Ratings ................................................................................. 417 Table 18.2 DC Characteristics ................................................................................................ 418 Table 18.3 Permissible Output Currents ................................................................................. 420 Table 18.4 Clock Timing ........................................................................................................ 421 Table 18.5 Control Signal Timing .......................................................................................... 422 Table 18.6 Timing of On-Chip Peripheral Modules ............................................................... 424 Table 18.7 A/D Conversion Characteristics............................................................................ 427 Table 18.8 Flash Memory Characteristics .............................................................................. 428
Rev. 0.5, 03/03, page xxvi of xxvi
Section 1 Overview
1.1 Features
* High-speed H8S/2600 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 69 basic instructions * Various peripheral functions 16-bit timer pulse unit (TPU) Watchdog timer Asynchronous or clocked synchronous serial communication interface (SCI) Hitachi controller area network (HCAN) 10-bit A/D converter Clock pulse generator * On-chip memory
ROM F-ZTAT Version Masked ROM version Model HD64F2615 HD6432615 ROM 64 kbytes 64 kbytes RAM 4 kbytes 4 kbytes In planning Remarks
* General I/O ports I/O pins: 39 Input-only pins: 17 * Supports various power-down modes * Compact package
Package QFP-80Q Code FP-80Q Body Size 14.0 Pin Pitch 0.65 mm
x 14.0 mm
Rev. 0.5, 03/03, page 1 of 438
1.2
Internal Block Diagram
VCL VCL VCC VCC VCC VSS VSS VSS
H8S/2600 CPU
Internal data bus
Internal address bus
Clock pulse generator
MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVSS
PA3/SCK2 PA2/RxD2 PA1/TxD2 PA0
PLL
Port A
RAM WDT x 2 channels HCAN x 1 channel
Port 1
P17/TIOCB2/TCLKD P16/TIOCA2/ P15/TIOCB1/TCLKC P14/TIOCA1/ P13/TIOCD0/TCLKB P12/TIOCC0/TCLKA P11/TIOCB0 P10/TIOCA0
TPU x 6 channels
A/D converter
Port 4
Port 9
P97 / AN15 P96 / AN14 P95 / AN13 P94 / AN12 P93 / AN11 P92 / AN10 P91 / AN9 P90 / AN8
Note: * The FWE pin is available only in the flash memory version. The NC pin is available only in the masked ROM version.
Rev. 0.5, 03/03, page 2 of 438
P47 / AN7 P46 / AN6 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0
Figure 1.1 Internal Block Diagram
AVCC AVSS
HRxD HTxD
Port D
SCI x 3 channels
Port C
PF7/ PF6 PF5 PF4 PF3/ PF2 PF1 PF0/
Port F
ROM (Mask ROM, flash memory)
Peripheral data bus
Peripheral address bus
Interrupt controller
Port B
FWE/NC* NMI
PB7/TIOCB5 PB6/TIOCA5 PB5/TIOCB4 PB4/TIOCA4 PB3/TIOCD3 PB2/TIOCC3 PB1/TIOCB3 PB0/TIOCA3 PC7 PC6 PC5/SCK1/ PC4/RxD1 PC3/TxD1 PC2/SCK0/ PC1/RxD0 PC0/TxD0
/
Bus controller
PD7 PD6 PD5 PD4
1.3
Pin Arrangement
P94/AN12 P95/AN13 P96/AN14 P97/AN15 PD4 PD5 PD6 PD7 VCL FWE/NC* Vss EXTAL Vcc XTAL PLLVss
AVcc P93/AN11 P92/AN10 P91/AN9 P90/AN8 P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 AVss P10/TIOCA0 Vcc P11/TIOCB0 Vss P12/TIOCC0/TCLKA VCL
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PLLVCL NMI PLLCAP
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
TOP VIEW (FP-80Q)
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
MD2 MD1 MD0 PA3/SCK2 PA2/RxD2 PA1/TxD2 PA0 PB7/TIOCB5 PB6/TIOCA5 PB5/TIOCB4 PB4/TIOCA4 PB3/TIOCD3 PB2/TIOCC3 Vcc PB1/TIOCB3 Vss PB0/TIOCA3 PC7 PC6 PC5/SCK1/
Note: * The FWE pin is available only in the flash memory version. The NC pin is available only in the masked ROM version.
P13/TIOCD0/TCLKB P14/TIOCA1/ P15/TIOCB1/TCLKC P16/TIOCA2/ P17/TIOCB2/TCLKD HTxD HRxD PF0/ PF1 PF2 / PF3/ PF4 PF5 PF6 PF7/ PC0/TxD0 PC1/RxD0 PC2/SCK0/ PC3/TxD1 PC4/RxD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 1.2 Pin Arrangement
Rev. 0.5, 03/03, page 3 of 438
1.4
Type Power supply
Pin Functions
Symbol VCC Pin No. 27 48 76 25 50 78 52 80 44 I/O Input Function Power supply pins. Connect all these pins to the system power supply. Ground pins. Connect all these pins to the system power supply (0 V). External capacitance pin for internal step-down power supply. Connect these pins to VSS via a 0.1-F capacitor (placed close to the pins). External capacitance pin for internal step-down power supply for an on-chip PLL oscillator. Connect this pin to PLLVSS via a 0.1-F capacitor (placed close to the pins). On-chip PLL oscillator ground pin. External capacitance pin for an on-chip PLL oscillator. For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 15, Clock Pulse Generator. For connection to a crystal resonator. An external clock can be input to the EXTAL pin. For examples of crystal resonator connection and external clock input, see section 15, Clock Pulse Generator. Supplies the system clock to external devices. Set the operating mode. Inputs at these pins should not be changed during operation. Reset input pin. When this pin is low, the chip is reset. When this pin is low, a transition is made to hardware standby mode. Pin for use by flash memory. This pin is only available in the flash memory version.
VSS
Input
VCL
Output
Clock
PLLVCL
Output
PLLVSS PLLCAP XTAL
46 42 47
Input Output Input
EXTAL
49
Input
Operating mode control System control MD2 MD1 MD0 RES STBY FWE
15 40 39 38 41 45 51
Output Input
Input Input Input
Rev. 0.5, 03/03, page 4 of 438
Type Interrupts
Symbol NMI IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
Pin No. 43 21 18 11 8 4 2 79 1 3 5 75 77 79 1 2 3 4 5 24 26 28 29 30 31 32 33 35 19 16 36 20 17 37 21 18 6 7
I/O Input Input
Function Nonmaskable interrupt request pin. If this pin is not used, it should be fixed high. These pins request a maskable interrupt.
16-bit timer pulse unit
TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5
Input
These pins input an external clock.
Input/ output
TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins.
Input/ output Input/ output Input/ output
TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins.
Input/ output Input/ output Output
TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins. TGRA_5 and TGRB_5 input capture input/output compare output/PWM output pins. Data output pins
Serial communication interface (SCI)/ smart card interface
TxD2 TxD1 TxD0 RxD2 RxD1 RxD0 SCK2 SCK1 SCK0
Input
Data input pins
Input/ Output Output Input
Clock input/output pins
HCAN
HTxD HRxD
CAN bus transmission pin CAN bus reception pin
Rev. 0.5, 03/03, page 5 of 438
Type A/D converter
Symbol AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 ADTRG AVCC
Pin No. 57 58 59 60 62 63 64 65 66 67 68 69 70 71 72 73 11 61
I/O Input
Function Analog input pins
Input Input
Pin for input of an external trigger to start A/D conversion Power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). The ground pin for the A/D converter. Connect this pin to the system power supply (0 V). 8-bit input/output pins
AVSS I/O ports P17 P16 P15 P14 P13 P12 P11 P10 P47 P46 P45 P44 P43 P42 P41 P40
74 5 4 3 2 1 79 77 75 66 67 68 69 70 71 72 73
Input Input/ output
Input
8-bit input pins
Rev. 0.5, 03/03, page 6 of 438
Type I/O ports
Symbol P97 P96 P95 P94 P93 P92 P91 P90 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
Pin No. 57 58 59 60 62 63 64 65 37 36 35 34 33 32 31 30 29 28 26 24 23 22 21 20 19 18 17 16 53 54 55 56 15 14 13 12 11 10 9 8
I/O Input
Function 8-bit input pins
Input/ output
4-bit input/output pins
Input/ output
8-bit input/output pins
Input/ output
8-bit input/output pins
Input/ output
4-bit input/output pins
Input/ output
8-bit input/output pins
Rev. 0.5, 03/03, page 7 of 438
Rev. 0.5, 03/03, page 8 of 438
Section 2 CPU
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
Features
* Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPUs object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract 8 x 8-bit register-register multiply 16 / 8-bit register-register divide 32 / 16-bit register-register divide : 3 states : 12 states : 20 states
Rev. 0.5, 03/03, page 9 of 438
: 1 state
16 x 16-bit register-register multiply : 4 states
* Two CPU operating modes Normal mode* Advanced mode * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported by the H8S/2600 CPU only. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600 CPU only. * The number of execution states of the MULXU and MULXS instructions;
Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21
In addition, there are differences in address space, CCR and EXR register functions, and powerdown modes, etc., depending on the model.
Rev. 0.5, 03/03, page 10 of 438
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements: * Additional control register One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast.
Rev. 0.5, 03/03, page 11 of 438
2.2
CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space A maximum address space of 64 kbytes can be accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table differs depending on the microcontroller. For details on the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI.
Rev. 0.5, 03/03, page 12 of 438
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector (Reserved for system use)
(Reserved for system use)
Exception vector table
Exception vector 1 Exception vector 2
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC (16 bits)
SP (SP *
2
EXR*1 Reserved*1*3 ) CCR CCR*3 PC (16 bits)
(a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning.
(b) Exception Handling
Figure 2.2 Stack Structure in Normal Mode 2.2.2 Advanced Mode
* Address Space Linear access is provided to a 16-Mbyte maximum address space is provided. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used.
Rev. 0.5, 03/03, page 13 of 438
* Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details on the exception vector table, see section 4, Exception Handling.
H'00000000 Reserved Exception vector 1 H'00000003 H'00000004 Reserved Exception vector 2 H'00000007 H'00000008 Reserved Exception vector table Exception vector 3 H'0000000B H'0000000C Reserved Exception vector 4 H'00000010 Reserved Exception vector 5
Figure 2.3 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. * Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
Rev. 0.5, 03/03, page 14 of 438
SP SP Reserved PC (24 bits) (SP *2 )
EXR*1 Reserved*1*3 CCR PC (24 bits)
(a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning.
(b) Exception Handling
Figure 2.4 Stack Structure in Advanced Mode
Rev. 0.5, 03/03, page 15 of 438
2.3
Address Space
Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
H'0000 64-kbyte H'FFFF H'00000000 16-Mbyte Program area
H'00FFFFFF
Data area
Cannot be used in this LSI
H'FFFFFFFF (a) Normal Mode (b) Advanced Mode
Figure 2.5 Memory Map
Rev. 0.5, 03/03, page 16 of 438
2.4
Register Configuration
The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC).
General Registers (Rn) and Extended Registers (En)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers (CR)
23 PC 0
EXR T
76543210 - - - - I2 I1 I0
76543210
CCR I UI H U N Z V C 63 MAC 31 Sign extension MACL 0 41 MACH 32
Legend
SP PC EXR T I2 to I0 CCR I UI :Stack pointer :Program counter :Extended control register :Trace bit :Interrupt mask bits :Condition-code register :Interrupt mask bit :User bit or interrupt mask bit H U N Z V C MAC :Half-carry flag :User bit :Negative flag :Zero flag :Overflow flag :Carry flag :Multiply-accumulate register
Figure 2.6 CPU Registers
Rev. 0.5, 03/03, page 17 of 438
2.4.1
General Registers
The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack.
* Address registers * 32-bit registers * 16-bit registers * 8-bit registers
E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H)
Figure 2.7 Usage of General Registers
Rev. 0.5, 03/03, page 18 of 438
Free area SP (ER7)
Stack area
Figure 2.8 Stack 2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR)
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions, except for the STC instruction, are executed, all interrupts including NMI will be masked for three states after execution is completed.
Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 I2 I1 I0 All 1 1 1 1 R/W R/W R/W Reserved These bits are always read as 1. These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller.
Rev. 0.5, 03/03, page 19 of 438
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Rev. 0.5, 03/03, page 20 of 438
Bit 1
Bit Name V
Initial Value Undefined
R/W R/W
Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
0
C
Undefined
R/W
Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
2.4.5
Multiply-Accumulate Register (MAC)
This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.6 Initial Values of CPU Registers
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.
Rev. 0.5, 03/03, page 21 of 438
2.5
Data Formats
The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats
Figure 2.9 shows the data formats in general registers.
Data Type
1-bit data
Register Number
RnH
Data Format
7 0 Don't care 76 54 32 10
7 1-bit data RnL Don't care
0
76 54 32 10
7 4-bit BCD data RnH Upper
43 Lower
0 Don't care
7 4-bit BCD data RnL Don't care Upper
43 Lower
0
7 Byte data RnH MSB
0 Don't care LSB 7 0 LSB
Byte data
RnL
Don't care MSB
Figure 2.9 General Register Data Formats (1)
Rev. 0.5, 03/03, page 22 of 438
Data Type Word data
Register Number Rn
Data Format
15
0
MSB
LSB
Word data
15
En
0
MSB
LSB
Longword data
31
ERn
16 15 0
MSB
En
Rn
LSB
Legend
ERn En Rn RnH RnL LSB : General register ER : General register E : General register R : General register RH : General register RL : Least significant bit
MSB : Most significant bit
Figure 2.9 General Register Data Formats (2)
Rev. 0.5, 03/03, page 23 of 438
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 is used as an address register to access the stack, the operand size should be word or longword.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Format
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M+1
MSB LSB
Longword data
Address 2N Address 2N+1 Address 2N+2 Address 2N+3
MSB
LSB
Figure 2.10 Memory Data Formats
Rev. 0.5, 03/03, page 24 of 438
2.6
Instruction Set
The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.1
Function Data transfer
Instruction Classification
Instructions MOV POP* , PUSH* LDM, STM MOVFPE* , MOVTPE*
3 3 1 1
Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B -- B/W/L
Types 5
Arithmetic operations
ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
4
23
MAC, LDMAC, STMAC, CLRMAC Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT
4 8 14 5 9 1
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* , JMP, BSR, JSR, RTS
2
B --
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- --
Block data transfer EEPMOV
Total: 69 Notes: B-byte; W-word; L-longword. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 0.5, 03/03, page 25 of 438
2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2
Symbol Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: *
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev. 0.5, 03/03, page 26 of 438
Table 2.3
Instruction MOV
Data Transfer Instructions
Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
LDM STM Note: *
L L
Refers to the operand size. B: Byte W: Word L: Longword
Rev. 0.5, 03/03, page 27 of 438
Table 2.4
Instruction ADD SUB
Arithmetic Operations Instructions (1)
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU
B
B/W/L
L B
B/W
MULXS
B/W
DIVXU
B/W
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
Rev. 0.5, 03/03, page 28 of 438
Table 2.4
Instruction DIVXS
Arithmetic Operations Instructions (2)
Size* B/W
1
Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. (EAs) x (EAd) + MAC MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits x 16 bits + 32 bits 32 bits, saturating 16 bits x 16 bits + 42 bits 42 bits, non-saturating 0 MAC Clears the multiply-accumulate register to zero. Rs MAC, MAC Rd Transfers data between a general register and a multiply-accumulate register.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
TAS* MAC
2
B --
CLRMAC LDMAC STMAC Note:
-- L
1. Refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 0.5, 03/03, page 29 of 438
Table 2.5
Instruction AND
Logic Operations Instructions
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement of general register contents.
OR
B/W/L
XOR
B/W/L
NOT Note: *
B/W/L
Refers to the operand size. B: Byte W: Word L: Longword
Table 2.6
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: *
Shift Instructions
Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotations are possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible.
B/W/L
B/W/L
B/W/L
Refers to the operand size. B: Byte W: Word L: Longword
Rev. 0.5, 03/03, page 30 of 438
Table 2.7
Instruction BSET
Bit Manipulation Instructions (1)
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
BIOR
B
Note:
*
Refers to the operand size. B: Byte
Rev. 0.5, 03/03, page 31 of 438
Table 2.7
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B
1
Function C ( of ) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
BIXOR
B
BLD
B
BILD
B
BST
B
BIST
B
Note:
*
Refers to the operand size. B: Byte
Rev. 0.5, 03/03, page 32 of 438
Table 2.8
Instruction Bcc
Branch Instructions
Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1
JMP BSR JSR RTS
-- -- -- --
Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
Rev. 0.5, 03/03, page 33 of 438
Table 2.9
Instruction TRAPA RTE SLEEP LDC
System Control Instructions
Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically XORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter.
STC
B/W
ANDC ORC XORC NOP Note: *
B B B --
Refers to the operand size. B: Byte W: Word L: Longword
Rev. 0.5, 03/03, page 34 of 438
Table 2.10 Block Data Transfer Instructions
Instruction EEPMOV.B Size -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W
--
2.6.2
Basic Instruction Formats
This LSI instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats.
Rev. 0.5, 03/03, page 35 of 438
* Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branching condition of Bcc instructions.
(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA(disp) rn rm MOV.B @(d:16, Rn), Rm, etc.
(4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:16, etc.
Figure 2.11 Instruction Formats (Examples)
Rev. 0.5, 03/03, page 36 of 438
2.7
Addressing Modes and Effective Address Calculation
The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
2.7.1
Register Direct--Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn
The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added.
Rev. 0.5, 03/03, page 37 of 438
2.7.4
Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn
Register indirect with post-increment--@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. Register indirect with pre-decrement--@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges
Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode* H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF
Note: Normal mode is not available in this LSI.
Rev. 0.5, 03/03, page 38 of 438
2.7.6
Immediate--#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect--@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: Normal mode is not available in this LSI.
Rev. 0.5, 03/03, page 39 of 438
Specified by @aa:8
Branch address
Specified by @aa:8
Reserved Branch address
(a) Normal Mode*
Note: * Normal mode is not available in this LSI.
(a) Advanced Mode
Figure 2.12 Branch Address Specification in Memory Indirect Mode 2.7.9 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI.
Rev. 0.5, 03/03, page 40 of 438
Table 2.13 Effective Address Calculation (1)
No 1
Addressing Mode and Instruction Format
Register direct(Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op 2
rm
rn 31
General register contents
Register indirect(@ERn)
0
31
24 23
0
Don't care
op 3
r
Register indirect with displacement @(d:16,ERn) or @(d:32,ERn)
31
General register contents
0 31 24 23 0
op
r
disp 31
Sign extension
Don't care 0 disp
4
Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+
31
General register contents
0
31
24 23
0
Don't care
op
r 31
1, 2, or 4
*Register indirect with pre-decrement @-ERn
0
General register contents
31
24 23
0
Don't care op r
Operand Size Byte Word Longword 1, 2, or 4
Offset 1 2 4
Rev. 0.5, 03/03, page 41 of 438
Table 2.13 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8 op abs
31
24 23 H'FFFF
87
0
Don't care
@aa:16 op abs
31
24 23
16 15
0
Don't care Sign extension
@aa:24 op abs
31
24 23
0
Don't care
@aa:32 op abs 31 24 23 0
Don't care
6
Immediate
#xx:8/#xx:16/#xx:32 op IMM
Operand is immediate data.
7
Program-counter relative @(d:8,PC) @(d:16,PC)
23
PC contents
0
op
disp
23
Sign extension
0 disp 31 24 23 0
Don't care
8
Memory indirect @@aa:8 * Normal mode*
31 op abs H'000000 15
87 abs
0
0
Memory contents
31
24 23
16 15 H'00
0
Don't care
* Advanced mode
31 op abs 31
Memory contents
87 H'000000 abs
0 31 24 23 Don't care 0
0
Note: * Normal mode is not available in this LSI.
Rev. 0.5, 03/03, page 42 of 438
2.8
Processing States
The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.13 indicates the state transitions. * Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program Execution State In this state, the CPU executes program instructions in sequence. * Bus-Released State In a product which has a bus master other than the CPU, such as a data transfer controller (DTC), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further details, refer to section 16, Power-Down Modes.
Rev. 0.5, 03/03, page 43 of 438
Reset state*
igh
, i gh = H Low =
=H
Exception handling state
In reqterru ue pt st
Bus-released state
Request for exception handling
End of exception handling
s Bu est u req
Bus request
End of bus request
us fb d o st En eque r
SLEEP instruction Program halt state
Program execution state
Notes: From any state, a transition to hardware standby mode occurs when goes low. * From any state except hardware standby mode, a transition to the reset state occurs whenever goes low. A transition can also be made to the reset state when the watchdog timer overflows.
Figure 2.13 State Transitions
2.9
2.9.1
Usage Notes
Usage Notes on Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in bytes, then, after bit manipulation, they write data in bytes again. Therefore, special care is necessary to use these instructions for the registers and the ports that include write-only bit. The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time, if it is obvious that the flag has been set to 1 in the interrupt processing routine or other processing, there is no need to read the flag beforehand.
Rev. 0.5, 03/03, page 44 of 438
Section 3 MCU Operating Modes
3.1 Operating Mode Selection
This LSI supports only operating mode 7, that is, the advanced single-chip mode. The operating mode is determined by the setting of the mode pins (MD2 to MD0). Only mode 7 can be used in this LSI. Therefore, all mode pins must be fixed high, as shown in table 3.1. Do not change the mode pin settings during operation. Table 3.1 MCU Operating Mode Selection
External Data Bus On-Chip Initial ROM Width Enabled -- Max. Width --
MCU CPU Operating Operating MD2 MD1 MD0 Mode Description Mode 7 1 1 1 Advanced Single-chip mode mode
Rev. 0.5, 03/03, page 45 of 438
3.2
Register Descriptions
The following registers are related to the operating mode. * Mode control register (MDCR) * System control register (SYSCR) 3.2.1 Mode Control Register (MDCR)
MDCR monitors the current operating mode of this LSI.
Bit 7 6 to 3 Bit Name Initial Value 1 All 0 R/W R/W Descriptions Reserved Only 1 should be written to this bit. Reserved These bits are always read as 0 and cannot be modified. 2 1 0 MDS2 MDS1 MDS0 * * * R R R Mode Select 2 to 0 These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are readonly bits and they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. These latches are canceled by a reset.
Note:
*
The initial values are determined according to the settings of the MD2 to MD0 pins.
3.2.2
System Control Register (SYSCR)
SYSCR selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM.
Bit 7 Bit Name MACS Initial Value 0 R/W Descriptions MAC Saturation Selects either saturating or non-saturating calculation for the MAC instruction. 0: Non-saturating calculation for the MAC instruction 1: Saturating calculation for the MAC instruction
Rev. 0.5, 03/03, page 46 of 438
Bit 6 5 4
Bit Name INTM1 INTM0
Initial Value 0 0 0
R/W R/W R/W
Descriptions Reserved This bit is always read as 0 and cannot be modified. These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Setting prohibited 10: Interrupt control mode 2 11: Setting prohibited
3
NMIEG
0
R/W
NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input
2 1 0
RAME
0 0 1
R/W
Reserved These bits are always read as 0 and cannot be modified. RAM Enable Enables or disables on-chip RAM. The RAME bit is initialized when the reset status is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled
Rev. 0.5, 03/03, page 47 of 438
3.3
Pin Functions in Each Operating Mode
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, however external addresses cannot be accessed. All I/O ports are available for use as input/output ports. 3.3.1 Pin Functions
Table 3.2 shows their functions in mode 7. Table 3.2 Pin Functions in Each Operating Mode
Port Port 1 P10 P11 to P13 Port A Port B Port C Port D Port F PF7 PF6 to PF4 PF3 PF2 to PF0 Legend P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After reset PA3 to PA0 Mode 7 P P P P P P P*/C P
Rev. 0.5, 03/03, page 48 of 438
3.4
Address Map
Figure 3.1 shows the address map in each operating mode.
ROM: 64 kbytes, RAM: 4 kbytes Mode 7 Advanced single-chip mode H'000000 On-chip ROM (Flash memory/ masked ROM*) H'00FFFF
H'FFE000 On-chip RAM H'FFEFBF
H'FFF800 Internal I/O registers H'FFFF3F
H'FFFF60 H'FFFFBF H'FFFFC0 On-chip RAM H'FFFFFF Internal I/O registers
Note : * In planning
Figure 3.1 Address Map
Rev. 0.5, 03/03, page 49 of 438
Rev. 0.5, 03/03, page 50 of 438
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller. Table 4.1
Priority High
Exception Types and Priority
Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low.
1
Trace*
Starts when execution of the current instruction or exception handling ends, if the trace (T) bit in the EXR is set to 1 Starts when a direction transition occurs as the result of SLEEP instruction execution. Starts when execution of the current instruction or exception 2 handling ends, if an interrupt request has been issued*
3
Direct transition Interrupt Low Trap instruction *
Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state.
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes.
Rev. 0.5, 03/03, page 51 of 438
Table 4.2
Exception Handling Vector Table
Vector Address*
1
Exception Source Power-on reset Manual reset *
2
Vector Number 0 1 2 3 4
Normal Mode H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0019 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'00FE to H'00FF
Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'01FC to H'01FF
Reserved for system use
Trace Interrupt (direct transitions) Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved for system use
5 6 7 8 9 10 11 12 13 14 15
External interrupt
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5
16 17 18 19 20 21 22 23
Reserved for system use
3
Internal interrupt*
24 127
Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table.
Rev. 0.5, 03/03, page 52 of 438
4.3
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 9, Watchdog Timer (WDT). The interrupt control mode is 0 immediately after reset. 4.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset sequence.
Rev. 0.5, 03/03, page 53 of 438
Vector fetch
Prefetch of first Internal processing program instruction
Internal address bus
(1)
(3)
(5)
Internal read signal
Internal write signal Internal data bus
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
Rev. 0.5, 03/03, page 54 of 438
Vector fetch
Internal processing
Prefetch of first program instruction
*
*
*
Address bus
(1)
(3)
(5)
,
High
D15 D0
(2)
(4)
(6)
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Three program wait states are inserted.
Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled: Cannot be Used in this LSI) 4.3.2 Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 State of On-Chip Peripheral Modules after Reset Release
After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively, and all modules enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when the module stop mode is exited.
Rev. 0.5, 03/03, page 55 of 438
4.4
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.3 Status of CCR and EXR after Trace Exception Handling
CCR Interrupt Control Mode 0 2 1 Legend 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution I UI I2 to I0 EXR T
Trace exception handling cannot be used. -- -- 0
4.5
Interrupts
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved to the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address.
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4.6
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved to the stack. 2. The interrupt mask bit is updated and the T bit is cleared. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling
CCR Interrupt Control Mode 0 2 I 1 1 UI -- -- I2 to I0 -- -- EXR T -- 0
Legend 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution
Rev. 0.5, 03/03, page 57 of 438
4.7
Stack Status after Exception Handling
Figures 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
(a) Normal Modes*2
SP
EXR Reserved*1
SP
CCR CCR*1 PC(16 bits)
CCR CCR*1 PC(16 bits)
Interrupt control mode 0
Interrupt control mode 2
(b) Advanced Modes
SP
EXR Reserved*1
SP
CCR PC(24 bits)
CCR PC(24 bits)
Interrupt control mode 0 Note: 1. Ignored on return. 2. Normal modes are not available in this LSI.
Interrupt control mode 2
Figure 4.3 Stack Status after Exception Handling
Rev. 0.5, 03/03, page 58 of 438
4.8
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers:
PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of what happens when the SP value is odd.
Address
CCR SP PC
SP
R1L
H'FFFEFA H'FFFEFB
PC
H'FFFEFC H'FFFEFD H'FFFEFE
SP
H'FFFEFF
SP set to H'FFFEFF
TRAPA instruction executed Data saved above SP
MOV.B R1L, @-ER7 executed Contents of CCR lost
Legend CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.4 Operation when SP Value is Odd
Rev. 0.5, 03/03, page 59 of 438
Rev. 0.5, 03/03, page 60 of 438
Section 5 Interrupt Controller
5.1 Features
* Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Seven external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ0 to IRQ5.
Rev. 0.5, 03/03, page 61 of 438
A block diagram of the interrupt controller is shown in figure 5.1.
INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I Interrupt request Vector number
CPU
Internal interrupt request WOVI0 to SLE0
CCR I2 to I0 EXR
IPR Interrupt controller Legend ISCR IER ISR IPR SYSCR
: IRQ sense control register : IRQ enable register : IRQ status register : Interrupt priority register : System control register
Figure 5.1 Block Diagram of Interrupt Controller
Rev. 0.5, 03/03, page 62 of 438
5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller. Table 5.1
Name NMI IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
Pin Configuration
I/O Input Input Input Input Input Input Input Function Nonmaskable external interrupt Rising or falling edge can be selected Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected
5.3
Register Descriptions
The interrupt controller has the following registers. For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR). * System control register (SYSCR) * IRQ sense control register H (ISCRH) * IRQ sense control register L (ISCRL) * IRQ enable register (IER) * IRQ status register (ISR) * Interrupt priority register A (IPRA) * Interrupt priority register B (IPRB) * Interrupt priority register D (IPRD) * Interrupt priority register E (IPRE) * Interrupt priority register F (IPRF) * Interrupt priority register G (IPRG) * Interrupt priority register H (IPRH) * Interrupt priority register J (IPRJ) * Interrupt priority register K (IPRK) * Interrupt priority register M (IPRM)
Rev. 0.5, 03/03, page 63 of 438
5.3.1
Interrupt Priority Registers A, B, D to H, J, K, M (IPRA, IPRB, IPRD to IPRH, IPRJ, IPRK, IPRM)
IPR are ten 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of the corresponding interrupt.
Bit 7 6 5 4 Bit Name IPR6 IPR5 IPR4 Initial Value 0 1 1 1 R/W R/W R/W R/W Description Reserved These bits are always read as 0. Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 3 2 1 0 IPR2 IPR1 IPR0 0 1 1 1 R/W R/W R/W Reserved These bits are always read as 0. Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest)
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5.3.2
IRQ Enable Register (IER)
IER controls the enabling and disabling of interrupt requests IRQ0 to IRQ5.
Bit 7 6 5 Bit Name IRQ5E Initial Value 0 0 0 R/W R/W R/W R/W Description Reserved Only 0 should be written to these bits. IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. 1 IRQ1E 0 R/W IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. 0 IRQ0E 0 R/W IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1.
Rev. 0.5, 03/03, page 65 of 438
5.3.3
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCR selects the source that generates an interrupt request at pins IRQ0 to IRQ5.
Bit 15 to 12 11 10 Bit Name IRQ5SCB IRQ5SCA Initial Value All 0 0 0 R/W R/W R/W R/W Description Reserved Only 0 should be written to these bits. IRQ5 Sense Control B IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input level low 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input 9 8 IRQ4SCB IRQ4SCA 0 0 R/W R/W IRQ4 Sense Control B IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input level low 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 6 IRQ3SCB IRQ3SCA 0 0 R/W R/W IRQ3 Sense Control B IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input level low 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input
Rev. 0.5, 03/03, page 66 of 438
Bit 5 4
Bit Name IRQ2SCB IRQ2SCA
Initial Value 0 0
R/W R/W R/W
Description IRQ2 Sense Control B IRQ2 Sense Control A 00: Interrupt request generated at IRQ2 input level low 01: Interrupt request generated at falling edge of IRQ2 input 10: Interrupt request generated at rising edge of IRQ2 input 11: Interrupt request generated at both falling and rising edges of IRQ2 input
3 2
IRQ1SCB IRQ1SCA
0 0
R/W R/W
IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input level low 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input
1 0
IRQ0SCB IRQ0SCA
0 0
R/W R/W
IRQ0 Sense Control B IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input level low 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input
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5.3.4
IRQ Status Register (ISR)
ISR indicates the status of IRQ0 to IRQ5 interrupt requests.
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved Only 0 should be written to these bits. [Setting conditions] When the interrupt source selected by the ISCR registers occurs [Clearing conditions] * * Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (n=5 to 0)
*
5.4
5.4.1
Interrupt
External Interrupts
There are seven external interrupts: NMI and IRQ0 to IRQ5. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQ0 to IRQ5 Interrupts: Interrupts IRQ0 to IRQ5 are requested by an input signal at pins IRQ0 to IRQ5. Interrupts IRQ0 to IRQ5 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ0 to IRQ5. * Enabling or disabling of interrupt requests IRQ0 to IRQ5 can be selected with IER. * The interrupt priority level can be set with IPR.
Rev. 0.5, 03/03, page 68 of 438
* The status of interrupt requests IRQ0 to IRQ5 is indicated in ISR. ISR flags can be cleared to 0 by software. The detection of IRQ0 to IRQ5 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0; and use the pin as an I/O pin for another function. A block diagram of interrupts IRQ0 to IRQ5 is shown in figure 5.2.
IRQnE IRQnSCA, IRQnSCB IRQnF Edge / level detection circuit input S R Q IRQn interrupt request
Clear signal Note: n= 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5 5.4.2 Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR.
5.5
Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed.
Rev. 0.5, 03/03, page 69 of 438
Table 5.2
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector Address*
Interrupt Source
Origin of Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5
Vector Number 7 16 17 18 19 20 21 22 23 25 28 29 32 33 34 35 36 40 41 42 43 44 45 46 47
Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0064 H'0070 H'0074 H'0080 H'0084 H'0088 H'008C H'0090 H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC
IPR IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB6 to IPRB4 IPRB2 to IPRB0
Priority High
External pin NMI
--
Reserved for system use Reserved for system use
Watchdog timer 0 A/D Watchdog timer 1 TPU channel 0
WOVI0 ADI WOVI1 TGI0A TGI0B TGI0C TGI0D TCI0V
IPRD6 to IPRD4 IPRE2 to IPRE0 IPRE2 to IPRE0 IPRF6 to IPRF4
TPU channel 1
TGI1A TGI1B TCI1V TCI1U
IPRF2 to IPRF0
TPU channel 2
TGI2A TGI2B TCI2V TCI2U
IPRG6 to IPRG4
Low
Rev. 0.5, 03/03, page 70 of 438
Vector Address* Interrupt Source TPU channel 3 Origin of Interrupt Source TGI3A TGI3B TGI3C TGI3D TCI3V TPU channel 4 TGI4A TGI4B TCI4V TCI4U TPU channel 5 TGI5A TGI5B TCI5V TCI5U SCI channel 0 ERI0 RXI0 TXI0 TEI0 SCI channel 1 ERI1 RXI1 TXI1 TEI1 SCI channel 2 ERI2 RXI2 TXI2 TEI2 HCAN ERS0, OVR0 RM0 RM1 SLE0 -- Note: * Reserved for system use Vector Number 48 49 50 51 52 56 57 58 59 60 61 62 63 80 81 82 83 84 85 86 87 88 89 90 91 104 105 106 107 111 Advanced Mode H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'01A0 H'01A4 H'01A8 H'01AC H'01BC IPRM2 to IPRM0 Low IPRM6 to IPRM4 IPRK2 to IPRK0 IPRK6 to IPRK4 IPRJ2 to IPRJ0 IPRH2 to IPRH0 IPRH6 to IPRH4 IPR IPRG2 to IPRG0 Priority High
Lower 16 bits of the start address.
Rev. 0.5, 03/03, page 71 of 438
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes
Interrupt Mask Bits Description I The priorities of interrupt sources are fixed at the default settings. Interrupt sources, except for NMI, are masked by the I bit. 2 IPR I2 to I0 8 priority levels other than NMI can be set with IPR. 8-level interrupt mask control is performed by bits I2 to I0.
Interrupt Priority Setting Control Mode Registers 0 Default
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than for NMI are masked by the I bit of the CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
Rev. 0.5, 03/03, page 72 of 438
Program execution status
Interrupt generated? Yes Yes
No
NMI No No I=0 Yes Hold pending
No IRQ0 Yes IRQ1 Yes SLE0 Yes No
Save PC and CCR
I1
Read vector address
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
Rev. 0.5, 03/03, page 73 of 438
5.6.2
Interrupt Control Mode 2
In interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
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Program execution status
Interrupt generated? Yes Yes NMI No No
No
Level 7 interrupt? Yes Mask level 6 or below? Yes
Level 6 interrupt? No Yes
No
Level 1 interrupt? Mask level 5 or below? Yes Mask level 0? Yes No Yes
No
No
Save PC, CCR, and EXR
Hold pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 5.6.3 Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
Rev. 0.5, 03/03, page 75 of 438
Interrupt acceptance Internal operation stack Vector fetch Internal operation
Interrupt level determination Instruction Wait for end of instruction prefetch
Interrupt service routine instruction prefetch
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(1) (3) (5) (7) (9) (11) (13) (2) (4) (6) (8) (10) (12) (14) (6) (8) (9) (11) (10) (12) (13) (14) Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine
Interrupt request signal
Internal address bus
Internal read signal
Internal write signal
Figure 5.5 Interrupt Exception Handling
Internal data bus
(1)
Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4
5.6.4
Interrupt Response Times
Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.4 Interrupt Response Times
Normal Mode* Interrupt control mode 0
1 5
Advanced Mode Interrupt control mode 0 3 Interrupt control mode 2 3
No. 1 2 3 4 5 6
Execution Status Interrupt priority determination*
Interrupt control mode 2 3
3
Number of wait states until executing 1 to 19 +2*SI 1 to 19+2*SI 2 instruction ends* PC, CCR, EXR stack save Vector fetch Instruction fetch*
3 4
1 to 19+2*SI 1 to 19+2*SI 2*SK 2*SI 2*SI 2 12 to 32 3*SK 2*SI 2*SI 2 13 to 33
2*SK SI 2*SI 2 11 to 31
3*SK SI 2*SI 2 12 to 32
Internal processing*
Total (using on-chip memory) Notes: 1. 2. 3. 4. 5.
Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in this LSI.
Rev. 0.5, 03/03, page 77 of 438
Table 5.5
Number of States in Interrupt Handling Routine Execution Status
Object of Access External Device * 8 Bit Bus 16 Bit Bus 2-State Access 2 3-State Access 3+m
Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK
Internal Memory 1
2-State Access 4
3-State Access 6+2m
Legend m: Number of wait states in an external device access. Note:* Cannot be used in this LSI.
5.7
5.7.1
Usage Notes
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.6 shows an example in which the TGIEA bit in the TPU's TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
Rev. 0.5, 03/03, page 78 of 438
TIER_0 write cycle by CPU
TCIVexception handling
Internal address bus
TIER_0 address
Internal write signal
TCIEV
TCFV
TCIV interrupt signal
Figure 5.6 Contention between Interrupt Generation and Disabling 5.7.2 Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 When Interrupts are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
Rev. 0.5, 03/03, page 79 of 438
5.7.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
Rev. 0.5, 03/03, page 80 of 438
Section 6 Bus Controller
The H8S/2600 CPU is driven by a system clock, denoted by the symbol . The bus controller controls a memory cycle and a bus cycle. Different methods are used to access on-chip memory and on-chip peripheral modules.
6.1
Basic Timing
The period from one rising edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, three, or four states. Different methods are used to access on-chip memory, on-chip support modules, and the external address space. 6.1.1 On-Chip Memory Access Timing (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 6.1 shows the on-chip memory access cycle.
Bus cycle T1 Internal address bus Address
Read access
Internal read signal Internal data bus Read data
Write access
Internal write signal Internal data bus Write data
Figure 6.1 On-Chip Memory Access Cycle
BSC0000A_000020020200
Rev. 0.5, 03/03, page 81 of 438
6.1.2
On-Chip Peripheral Module Access Timing
The on-chip peripheral modules, except for HCAN are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. For details, refer to section 17, List of Registers. Figure 6.2 shows access timing for the on-chip peripheral modules.
Bus cycle T1 Internal address bus Address T2
Read access
Internal read signal Internal data bus Read data
Write access
Internal write signal Internal data bus Write data
Figure 6.2 On-Chip Support Module Access Cycle
Rev. 0.5, 03/03, page 82 of 438
6.1.3
On-Chip HCAN Module Access Timing
On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access timing is shown in figure 6.3.
Bus cycle T1 Internal address bus Address T2 T3 Tw Tw T4
HCAN read signal Read Internal data bus Read data
HCAN write signal Write Internal data bus Write data
Figure 6.3 On-Chip HCAN Module Access Cycle (Wait States Inserted)
Rev. 0.5, 03/03, page 83 of 438
Rev. 0.5, 03/03, page 84 of 438
Section 7 I/O Ports
Table 7.1 summarizes the port functions. The pins of each port also have other functions such as input/output or interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register. Ports A to D have a built-in input pull-up MOS function and an input pull-up MOS control register (PCR) to control the on/off state of the input pull-up MOS. Ports A to C include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. All the I/O ports can drive a single TTL load and a 30 pF capacitive load.
Rev. 0.5, 03/03, page 85 of 438
Table 7.1
Port Port 1
Port Functions
Description General I/O port also functioning as TPU I/O pins and interrupt input pins Port and Other Functions Name P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB P12/TIOCC0/TCLKA P11/TIOCB0 P10/TIOCA0 Input/Output and Output Type
Port 4
General input port also functioning as A/D converter analog inputs
P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
Port 9
General input port also functioning as A/D converter analog inputs
P97/AN15 P96/AN14 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8
Port A
General I/O port also functioning as SCI_2 I/O pins
PA3/SCK2 PA2/RxD2 PA1/TxD2 PA0
Built-in input pull-up MOS Push-pull or open-drain output selectable
Rev. 0.5, 03/03, page 86 of 438
Port Port B
Description General I/O port also functioning as TPU_5, TPU_4, and TPU_3 I/O pins
Port and Other Functions Name PB7/TIOCB5 PB6/TIOCA5 PB5/TIOCB4 PB4/TIOCA4 PB3/TIOCD3 PB2/TIOCC3 PB1/TIOCB3 PB0/TIOCA3
Input/Output and Output Type Built-in input pull-up MOS Push-pull or open-drain output selectable
Port C
General I/O port also functioning as SCI_1 and SCI_0 I/O pins, and interrupt input pins
PC7 PC6 PC5/SCK1/IRQ5 PC4/RxD1 PC3/TxD1 PC2/SCK0/IRQ4 PC1/RxD0 PC0/TxD0
Built-in input pull-up MOS Push-pull or open-drain output selectable
Port D
General I/O port
PD7 PD6 PD5 PD4 PF7/ PF6 PF5 PF4 PF3/ADTRG/IRQ3 PF2 PF1 PF0/IRQ2
Built-in input pull-up MOS
Port F
General I/O port also functioning as interrupt input pins, an A/D converter start trigger input pin, and a system clock output pin ()
Rev. 0.5, 03/03, page 87 of 438
7.1
Port 1
Port 1 is an 8-bit I/O port that also has other functions. Port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 register (PORT1) 7.1.1 Port 1 Data Direction Register (P1DDR)
P1DDR specifies the input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin. Clearing this bit to 0 makes the pin an input pin.
7.1.2
Port 1 Data Register (P1DR)
P1DR stores output data for port 1 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin is specified as a general purpose output port.
Rev. 0.5, 03/03, page 88 of 438
7.1.3
Port 1 Register (PORT1)
PORT1 shows the pin states of the port 1. PORT1 cannot be modified.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P17 P16 P15 P14 P13 P12 P11 P10 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read.
Determined by the states of pins P17 to P10.
7.1.4
Pin Functions
Port 1 pins also function as TPU I/O pins and interrupt input pins. The correspondence between the register specification and the pin functions is shown below. Table 7.2 P17 Pin Function
Output TIOCB2 output 0 P17 input TIOCB2 input TCLKD input Note: * For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). Input or Initial Value 1 P17 output
TPU Channel 2 Setting* P17DDR Pin function
Rev. 0.5, 03/03, page 89 of 438
Table 7.3
P16 Pin Function
Output TIOCA2 output 0 P16 input TIOCA2 input IRQ1 input Input or Initial Value 1 P16 output
TPU Channel 2 Setting* P16DDR Pin function
Note:
*
For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU).
Table 7.4
P15 Pin Function
Output TIOCB1 output 0 P15 input TIOCB1 input TCLKC input Input or Initial Value 1 P15 output
TPU Channel 1 Setting* P15DDR Pin function
Note:
*
For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU).
Table 7.5
P14 Pin Function
Output TIOCA1 output 0 P14 input TIOCA1 input IRQ0 input Input or Initial Value 1 P14 output
TPU Channel 1 Setting* P14DDR Pin function
Note:
*
For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU).
Rev. 0.5, 03/03, page 90 of 438
Table 7.6
P13 Pin Function
Output TIOCD0 output 0 P13 input TIOCD0 input TCLKB input Input or Initial Value 1 P13 output
TPU Channel 0 Setting* P13DDR Pin function
Note:
*
For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU).
Table 7.7
P12 Pin Function
Output TIOCC0 output 0 P12 input TIOCC0 input TCLKA input Input or Initial Value 1 P12 output
TPU Channel 0 Setting* P12DDR Pin function
Note:
*
For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU).
Table 7.8
P11 Pin Function
Output TIOCB0 output 0 P11 input TIOCB0 input Input or Initial Value 1 P11 output
TPU Channel 0 Setting* P11DDR Pin function Note: *
For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU).
Table 7.9
P10 Pin Function
Output TIOCA0 output 0 P10 input TIOCA0 input Input or Initial Value 1 P10 output
TPU Channel 0 Setting* P10DDR Pin function Note: *
For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). Rev. 0.5, 03/03, page 91 of 438
7.2
Port 4
Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins. Port 4 has the following register. * Port 4 register (PORT4) Port 4 Register (PORT4)
7.2.1
PORT4 shows port 4 pin states. PORT4 cannot be modified.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P47 P46 P45 P44 P43 P42 P41 P40 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description The pin states are always read when a port 4 read is performed.
Determined by the states of pins P47 to P40.
7.3
Port 9
Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins. Port 9 has the following register. * Port 9 register (PORT9) Port 9 Register (PORT9)
7.3.1
PORT9 shows port 9 pin states. PORT9 cannot be modified.
Rev. 0.5, 03/03, page 92 of 438
Bit 7 6 5 4 3 2 1 0
Bit Name P97 P96 P95 P94 P93 P92 P91 P90
Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined*
R/W R R R R R R R R
Description The pin states are always read when a port 9 read is performed.
Note:* Determined by the states of pins P97 to P90.
7.4
Port A
Port A is a 4-bit I/O port that also has other functions. Port A has the following registers. * Port A data direction register (PADDR) * Port A data register (PADR) * Port A register (PORTA) * Port A pull-up MOS control register (PAPCR) * Port A open-drain control register (PAODR) 7.4.1 Port A Data Direction Register (PADDR)
PADDR specifies whether the pins of port A are used for input or output. PADDR cannot be read; if it is, an undefined value will be read.
Bit 7 to 4 3 2 1 0 Bit Name PA3DDR PA2DDR PA1DDR PA0DDR Initial Value Undefined 0 0 0 0 R/W W W W W Description Reserved When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port A pin an output pin. Clearing this bit to 0 makes the pin an input pin.
Rev. 0.5, 03/03, page 93 of 438
7.4.2
Port A Data Register (PADR)
PADR stores output data for port A pins.
Bit 7 to 4 3 2 1 0 Bit Name PA3DR PA2DR PA1DR PA0DR Initial Value Undefined 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved The read value is undefined. Output data for a pin is stored when the pin is specified as a general purpose output port.
7.4.3
Port A Register (PORTA)
PORTA shows port A pin states. PORTA cannot be modified.
Bit 7 to 4 3 2 1 0 Note: Bit Name PA3 PA2 PA1 PA0 * Initial Value Undefined Undefined* Undefined* Undefined* Undefined* R/W R R R R Description Reserved The read value is undefined. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read.
Determined by the states of pins PA3 to PA0.
Rev. 0.5, 03/03, page 94 of 438
7.4.4
Port A Pull-Up MOS Control Register (PAPCR)
PAPCR controls the on/off state of the input pull-up MOS of port A.
Bit 7 to 4 3 2 1 0 Bit Name PA3PCR PA2PCR PA1PCR PA0PCR Initial Value Undefined 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved The read value is undefined. When a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
7.4.5
Port A Open-Drain Control Register (PAODR)
PAODR specifies the output type of port A.
Bit 7 to 4 3 2 1 0 Bit Name PA3ODR PA2ODR PA1ODR PA0ODR Initial Value Undefined 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved The read value is undefined. When a pin is specified as an output port, setting the corresponding bit to 1 specifies pin output to opendrain and the PMOS to the off state. Clearing this bit to 0 specifies that to push-pull output.
Rev. 0.5, 03/03, page 95 of 438
7.4.6
Pin Functions
Port A pins also function as SCI_2 I/O pins. The correspondence between the register specification and the pin functions is shown below. Table 7.10 PA3 Pin Function
CKE1 C/A CKE0 PA3DDR Pin function 0 PA3 input 0 1 PA3 output 0 1 SCK2 output 0 1 SCK2 output 1 SCK2 input
Table 7.11 PA2 Pin Function
RE PA2DDR Pin function 0 PA2 input 0 1 PA2 output 1 RxD2 input
Table 7.12 PA1 Pin Function
TE PA1DDR Pin function 0 PA1 input 0 1 PA1 output 1 TxD2 output
Table 7.13 PA0 Pin Function
PA0DDR Pin function 0 PA0 input 1 PA0 output
7.5
Port B
Port B is an 8-bit I/O port that also has other functions. Port B has the following registers. * Port B data direction register (PBDDR) * Port B data register (PBDR) * Port B register (PORTB) * Port B pull-up MOS control register (PBPCR) * Port B open-drain control register (PBODR)
Rev. 0.5, 03/03, page 96 of 438
7.5.1
Port B Data Direction Register (PBDDR)
PBDDR specifies whether the pins of port B are used for input or output. PBDDR cannot be read; if it is, an undefined value will be read.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin. Clearing this bit to 0 makes the pin an input pin.
7.5.2
Port B Data Register (PBDR)
PBDR stores output data for the port B pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin is specified as a general purpose output port.
Rev. 0.5, 03/03, page 97 of 438
7.5.3
Port B Register (PORTB)
PORTB shows port B pin states. PORTB cannot be modified.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read.
Determined by the states of pins PB7 to PB0.
7.5.4
Port B Pull-Up MOS Control Register (PBPCR)
PBPCR controls the on/off state of the input pull-up MOS of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
Rev. 0.5, 03/03, page 98 of 438
7.5.5
Port B Open-Drain Control Register (PBODR)
PBODR specifies the output type of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin function is specified as an output port, setting the corresponding bit to 1 specifies pin output as open-drain and the PMOS to the off state. Clearing this bit to 0 specifies push-pull output.
7.5.6
Pin Functions
Port B pins also function as TPU I/O pins. The correspondence between the register specification and the pin functions is shown below. Table 7.14 PB7 Pin Function
TPU channel 5 setting* PB7DDR Pin function Note: * Output TIOCB5 output 0 PB7 input TIOCB5 input For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). Input or Initial Value 1 PB7 output
Table 7.15 PB6 Pin Function
TPU channel 5 setting* PB6DDR Pin function Note: * Output Input or Initial Value 0 PB6 input TIOCA5 input For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). 1 PB6 output
-
TIOCA5 output
Rev. 0.5, 03/03, page 99 of 438
Table 7.16 PB5 Pin Function
TPU channel 4 setting* PB5DDR Pin function Note: * Output TIOCB4 output 0 PB5 input TIOCB4 input For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). Input or Initial Value 1 PB5 output
Table 7.17 PB4 Pin Function
TPU channel 4 setting* PB4DDR Pin function Note: * Output TIOCA4 output 0 PB4 input TIOCA4 input For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). Input or Initial Value 1 PB4 output
Table 7.18 PB3 Pin Function
TPU channel 3 setting* PB3DDR Pin function Note: * Output TIOCD3 output 0 PB3 input TIOCD3 input For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). Input or Initial Value 1 PB3 output
Table 7.19 PB2 Pin Function
TPU channel 3 setting* PB2DDR Pin function Note: * Output TIOCC3 output 0 PB2 input TIOCC3 input For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). Input or Initial Value 1 PB2 output
Rev. 0.5, 03/03, page 100 of 438
Table 7.20 PB1 Pin Function
TPU channel 3 setting* PB1DDR Pin function Note: * Output TIOCB3 output 0 PB1 input TIOCB3 input For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). Input or Initial Value 1 PB1 output
Table 7.21 PB0 Pin Function
TPU channel 3 setting* PB0DDR Pin function Note: * Output TIOCA3 output 0 PB0 input TIOCA3 input For details on the TPU channel specification, refer to section 8, 16-Bit Timer Pulse Unit (TPU). Input or Initial Value 1 PB0 output
7.6
Port C
Port C is an 8-bit I/O port that also has other functions. Port C has the following registers. * Port C data direction register (PCDDR) * Port C data register (PCDR) * Port C register (PORTC) * Port C pull-up MOS control register (PCPCR) * Port C open-drain control register (PCODR) 7.6.1 Port C Data Direction Register (PCDDR)
PCDDR specifies whether the pins of port C are used for input or output. PCDDR cannot be read; if it is, an undefined value will be read.
Rev. 0.5, 03/03, page 101 of 438
Bit 7 6 5 4 3 2 1 0
Bit Name PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial Value 0 0 0 0 0 0 0 0
R/W W W W W W W W W
Description When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin. Clearing this bit to 0 makes the pin an input pin.
7.6.2
Port C Data Register (PCDR)
PCDR stores output data for the port C pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin is specified as a general purpose output port.
Rev. 0.5, 03/03, page 102 of 438
7.6.3
Port C Register (PORTC)
PORTC shows port C pin states. PORTC cannot be modified.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read.
Determined by the states of pins PC7 to PC0.
7.6.4
Port C Pull-Up MOS Control Register (PCPCR)
PCPCR controls the on/off state of the input pull-up MOS of port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
Rev. 0.5, 03/03, page 103 of 438
7.6.5
Port C Open-Drain Control Register (PCODR)
PCODR specifies an output type of port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin is specified as an output port, setting the corresponding bit to 1 specifies pin output as opendrain and the PMOS to the off state. Clearing this bit to 0 specifies push-pull output.
7.6.6
Pin Functions
Port C pins also function as SCI_1 and SCI_0 I/O and interrupt input. The correspondence between the register specification and the pin functions is shown below. Table 7.22 PC7 Pin Function
PC7DDR Pin function 0 PC7 input 1 PC7 output
Table 7.23 PC6 Pin Function
PC6DDR Pin function 0 PC6 input 1 PC6 output
Table 7.24 PC5 Pin Function
CKE1 C/A CKE0 PC5DDR Pin function 0 PC5 input IRQ5 input 0 1 PC5 output 0 1 SCK1 output 0 1 SCK1 output 1 SCK1 input
Rev. 0.5, 03/03, page 104 of 438
Table 7.25 PC4 Pin Function
RE PC4DDR Pin function 0 PC4 input 0 1 PC4 output 1 RxD1 input
Table 7.26 PC3 Pin Function
TE PC3DDR Pin function 0 PC3 input 0 1 PC3 output 1 TxD1 output
Table 7.27 PC2 Pin Function
CKE1 C/A CKE0 PC2DDR Pin function 0 PC2 input IRQ4 input 0 1 PC2 output 0 1 SCK0 output 0 1 SCK0 output 1 SCK0 input
Table 7.28 PC1 Pin Function
RE PC1DDR Pin function 0 PC1 input 0 1 PC1 output 1 RxD0 input
Table 7.29 PC0 Pin Function
TE PC0DDR Pin function 0 PC0 input 0 1 PC0 output 1 TxD0 output
Rev. 0.5, 03/03, page 105 of 438
7.7
Port D
Port D is a 4-bit I/O port that also has other functions. Port D has the following registers. * Port D data direction register (PDDDR) * Port D data register (PDDR) * Port D register (PORTD) * Port D pull-up MOS control register (PDPCR) 7.7.1 Port D Data Direction Register (PDDDR)
PDDDR specifies whether the pins of port D are used for input or output. PDDDR cannot be read; if it is, an undefined value will be read.
Bit 7 6 5 4 3 to 0 Bit Name PD7DDR PD6DDR PD5DDR PD4DDR Initial Value 0 0 0 0 Undefined R/W W W W W Reserved The write value should always be 0. Description When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin. Clearing this bit to 0 makes the pin an input pin.
Rev. 0.5, 03/03, page 106 of 438
7.7.2
Port D Data Register (PDDR)
PDDR stores output data for the port D pins.
Bit 7 6 5 4 3 to 0 Bit Name PD7DR PD6DR PD5DR PD4DR Initial Value 0 0 0 0 Undefined R/W R/W R/W R/W R/W Reserved The read value is undefined. Description Output data for a pin is stored when the pin is specified as a general purpose output port.
7.7.3
Port D Register (PORTD)
PORTD shows port D pin states. PORTD cannot be modified.
Bit 7 6 5 4 3 to 0 Note: Bit Name PD7 PD6 PD5 PD4 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined R/W R R R R Reserved The read value is undefined. Determined by the states of pins PD7 to PD4. Description If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read.
Rev. 0.5, 03/03, page 107 of 438
7.7.4
Port D Pull-up MOS Control Register (PDPCR)
PDPCR controls on/off states of the input pull-up MOS of port D.
Bit 7 6 5 4 3 to 0 Bit Name PD7PCR PD6PCR PD5PCR PD4PCR Initial Value 0 0 0 0 Undefined R/W R/W R/W R/W R/W Reserved The write value should always be 0. Description When the pin is in its input state, the input pull-up MOS of the input pin is on when the corresponding bit is set to 1.
7.7.5
Pin Function
Port D is a 4-bit I/O port. Table 7.30 PDn Pin Function
PDnDDR Pin function Legend: n = 7 to 4 0 PDn input 1 PDn output
7.8
Port F
Port F is an 8-bit I/O port that also has other functions. Port F has the following registers. * Port F data direction register (PFDDR) * Port F data register (PFDR) * Port F register (PORTF) 7.8.1 Port F Data Direction Register (PFDDR)
PFDDR specifies whether the pins of port F are used for input or output. PFDDR cannot be read; if it is, an undefined value will be read.
Rev. 0.5, 03/03, page 108 of 438
Bit 7
Bit Name PF7DDR
Initial Value 0
R/W W
Description When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the PF7 pin a output pin. Clearing this bit to 0 makes the pin an input pin. When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding port F pin an output pin. Clearing this bit to 0 makes the pin an input pin.
6 5 4 3 2 1 0
PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
0 0 0 0 0 0 0
W W W W W W W
7.8.2
Port F Data Register (PFDR)
PFDR stores output data for the port F pins.
Bit 7 6 5 4 3 2 1 0 Bit Name -- PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. Output data for a pin is stored when the pin is specified as a general purpose output port.
Rev. 0.5, 03/03, page 109 of 438
7.8.3
Port F Register (PORTF)
PORTF shows port F pin states. PORTF cannot be modified.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read.
Determined by the states of pins PF7 to PF0.
7.8.4
Pin Functions
Port F pins also function as external interrupt input (IRQ2 and IRQ3), A/D trigger input (ADTRG), and system clock output (). The correspondence between the register specification and the pin functions is shown below. Table 7.31 PF7 Pin Function
PF7DDR Pin function 0 PF7 input 1 output
Table 7.32 PF6 Pin Function
PF6DDR Pin function 0 PF6 input 1 PF6 output
Table 7.33 PF5 Pin Function
PF5DDR Pin function 0 PF5 input 1 PF5 output
Rev. 0.5, 03/03, page 110 of 438
Table 7.34 PF4 Pin Function
PF4DDR Pin function 0 PF4 input 1 PF4 output
Table 7.35 PF3 Pin Function
PF3DDR Pin function 0 PF3 input ADTRG input* IRQ3 input*
2 1
1 PF3 output
Notes: 1. ADTRG input when TRGS0 = TRGS1 = 1. 2. When used as an external interrupt input pin, do not use as an I/O pin for another function.
Table 7.36 PF2 Pin Function
PF2DDR Pin function 0 PF2 input 1 PF2 output
Table 7.37 PF1 Pin Function
PF1DDR Pin function 0 PF1 input 1 PF1 output
Table 7.38 PF0 Pin Function
PF0DDR Pin function 0 PF0 input IRQ2 input 1 PF0 output
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Section 8 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 8.1 and figure 8.1, respectively.
8.1
Features
* Maximum 16-pulse input/output * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 15-phase PWM output is possible in combination with synchronous operation * Buffer operation settable for channels 0 and 3 * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 * Cascaded operation * Fast access via internal 16-bit bus * 26 interrupt sources * Automatic transfer of register data * A/D converter conversion start trigger can be generated * Module stop mode can be set
TIMTPU0A_000020020200
Rev. 0.5, 03/03, page 113 of 438
Table 8.1
Item Count clock
TPU Functions
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture /1 /4 /16 /64 /256 TCLKA TCLKB TGRA_1 TGRB_1 -- TIOCA1 TIOCB1 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 -- TIOCA2 TIOCB2 /1 /4 /16 /64 /256 /1024 /4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture /1 /4 /16 /64 /1024 TCLKA TCLKC TGRA_4 TGRB_4 -- TIOCA4 TIOCB4 /1 /4 /16 /64 /256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 -- TIOCA5 TIOCB5
General registers General registers/ buffer registers I/O pins
Counter clear function
TGR compare match or input capture
TGR compare match or input capture
TGR compare match or input capture
TGR compare match or input capture
Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation -- -- -- -- -- --
Rev. 0.5, 03/03, page 114 of 438
Item
Channel 0
Channel 1 TGRA_1 compare match or input capture 4 sources
Channel 2 TGRA_2 compare match or input capture 4 sources
Channel 3 TGRA_3 compare match or input capture 5 sources
Channel 4 TGRA_4 compare match or input capture 4 sources
Channel 5 TGRA_5 compare match or input capture 4 sources Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow
A/D TGRA_0 converter compare trigger match or input capture Interrupt sources 5 sources *
Compare * match or input capture 0A Compare * match or input capture 0B Compare * match or * input capture 0C Compare match or input capture 0D Overflow
Compare * match or input capture 1A Compare * match or input capture 1B Overflow * Underflow *
Compare * match or input capture 2A Compare * match or input capture 2B Overflow * Underflow
Compare * match or input capture 3A Compare * match or input capture 3B Compare * match or * input capture 3C Compare match or input capture 3D Overflow
Compare * match or input capture 4A Compare * match or input capture 4B Overflow * Underflow *
*
*
*
*
*
*
Legend : Possible -- : Not possible
Rev. 0.5, 03/03, page 115 of 438
TIORH TIORL
TMDR
Channel 3
TSR
TGRC
TGRD
TGRA
TGRB
TCNT
Input/output pins Channel 3:
TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5
Control logic for channels 3 to 5
TIOR
Channel 5:
TMDR
Channel 5
TSR
TIER
TCR
Channel 4:
TGRA
TIOR
Clock input Internal clock:
/1 /4 /16 /64 /256 /1024 /4096 TCLKA TCLKB TCLKC TCLKD
TIER
TCR
Module data bus
TSYR
TGRB
TCNT
Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCIV3 Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U
TMDR
Channel 4
TSR
TIER
TCR
TGRA
TGRB
TCNT
Control logic
Internal data bus
Bus interface
Common
External clock:
TMDR
Channel 2
TSR
TSTR
A/D converter convertion start signal
TGRA
TIOR
Input/output pins Channel 0:
TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2
TIER
TCR
TGRB
TCNT
Channel 2:
TIORH TIORL
TMDR
Channel 0
TSR
TIER
TCR
Channel 1:
Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U
TMDR
Control logic for channel 0 to 2
Channel 1
TSR
TGRA
TIOR
TGRB TGRC TGRD TGRB
TCNT TCNT
Legend TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register TIOR(H, L) TIER: TSR: TGR(A, B, C, D): Timer I/O control registers (H, L) Timer interrupt enable register Timer status register TImer general registers (A, B, C, D)
Figure 8.1 Block Diagram of TPU
Rev. 0.5, 03/03, page 116 of 438
TIER
TCR
TGRA
8.2
Table 8.2
Channel All
Input/Output Pins
Pin Configuration
Symbol TCLKA TCLKB TCLKC TCLKD I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 and 5 phase counting mode A phase input) External clock B input pin (Channel 1 and 5 phase counting mode B phase input) External clock C input pin (Channel 2 and 4 phase counting mode A phase input) External clock D input pin (Channel 2 and 4 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRA_5 input capture input/output compare output/PWM output pin TGRB_5 input capture input/output compare output/PWM output pin
0
TIOCA0 TIOCB0 TIOCC0 TIOCD0
1
TIOCA1 TIOCB1
2
TIOCA2 TIOCB2
3
TIOCA3 TIOCB3 TIOCC3 TIOCD3
4
TIOCA4 TIOCB4
5
TIOCA5 TIOCB5
Rev. 0.5, 03/03, page 117 of 438
8.3
Register Descriptions
The TPU has the following registers for each channel. * Timer control register_0 (TCR_0) * Timer mode register_0 (TMDR_0) * Timer I/O control register H_0 (TIORH_0) * Timer I/O control register L_0 (TIORL_0) * Timer interrupt enable register_0 (TIER_0) * Timer status register_0 (TSR_0) * Timer counter_0 (TCNT_0) * Timer general register A_0 (TGRA_0) * Timer general register B_0 (TGRB_0) * Timer general register C_0 (TGRC_0) * Timer general register D_0 (TGRD_0) * Timer control register_1 (TCR_1) * Timer mode register_1 (TMDR_1) * Timer I/O control register _1 (TIOR_1) * Timer interrupt enable register_1 (TIER_1) * Timer status register_1 (TSR_1) * Timer counter_1 (TCNT_1) * Timer general register A_1 (TGRA_1) * Timer general register B_1 (TGRB_1) * Timer control register_2 (TCR_2) * Timer mode register_2 (TMDR_2) * Timer I/O control register_2 (TIOR_2) * Timer interrupt enable register_2 (TIER_2) * Timer status register_2 (TSR_2) * Timer counter_2 (TCNT_2) * Timer general register A_2 (TGRA_2) * Timer general register B_2 (TGRB_2) * Timer control register_3 (TCR_3) * Timer mode register_3 (TMDR_3) * Timer I/O control register H_3 (TIORH_3) * Timer I/O control register L_3 (TIORL_3) * Timer interrupt enable register_3 (TIER_3) * Timer status register_3 (TSR_3) * Timer counter_3 (TCNT_3)
Rev. 0.5, 03/03, page 118 of 438
* Timer general register A_3 (TGRA_3) * Timer general register B_3 (TGRB_3) * Timer general register C_3 (TGRC_3) * Timer general register D_3 (TGRD_3) * Timer control register_4 (TCR_4) * Timer mode register_4 (TMDR_4) * Timer I/O control register _4 (TIOR_4) * Timer interrupt enable register_4 (TIER_4) * Timer status register_4 (TSR_4) * Timer counter_4 (TCNT_4) * Timer general register A_4 (TGRA_4) * Timer general register B_4 (TGRB_4) * Timer control register_5 (TCR_5) * Timer mode register_5 (TMDR_5) * Timer I/O control register_5 (TIOR_5) * Timer interrupt enable register_5 (TIER_5) * Timer status register_5 (TSR_5) * Timer counter_5 (TCNT_5) * Timer general register A_5 (TGRA_5) * Timer general register B_5 (TGRB_5) Common Registers * Timer start register (TSTR) * Timer synchro register (TSYR)
Rev. 0.5, 03/03, page 119 of 438
8.3.1
Timer Control Register (TCR)
TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel (channel 0 to 5). TCR register settings should be conducted only when TCNT operation is stopped.
Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 8.3 and 8.4 for details. Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges Legend X: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 8.5 to 8.10 for details.
Rev. 0.5, 03/03, page 120 of 438
Table 8.3
Channel 0, 3
CCLR0 to CCLR2 (channels 0 and 3)
Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input 2 capture* TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation*
1
0
0 1
1
0 1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Table 8.4
Channel 1, 2, 4, 5
CCLR0 to CCLR2 (channels 1, 2, 4, and 5)
Bit 7 Bit 6 2 Reserved* CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation*
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified.
Rev. 0.5, 03/03, page 121 of 438
Table 8.5
Channel 0
TPSC0 to TPSC2 (channel 0)
Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input
Table 8.6
Channel 1
TPSC0 to TPSC2 (channel 1)
Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
Rev. 0.5, 03/03, page 122 of 438
Table 8.7
Channel 2
TPSC0 to TPSC2 (channels 2)
Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 8.8
Channel 3
TPSC0 to TPSC2 (channel 3)
Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input Internal clock: counts on /1024 Internal clock: counts on /256 Internal clock: counts on /4096
Rev. 0.5, 03/03, page 123 of 438
Table 8.9
Channel 4
TPSC0 to TPSC2 (channel 4)
Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
Table 8.10 TPSC0 to TPSC2 (channel 5)
Channel 5 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /256 External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode.
Rev. 0.5, 03/03, page 124 of 438
8.3.2
Timer Mode Register (TMDR)
TMDR sets the operating mode of each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped.
Bit 7 6 5 Bit Name BFB Initial value 1 1 0 R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 0 to 3 These bits are used to set the timer operating mode. MD3 is a reserved bit. In a write, it should always be written with 0. See table 8.11 for details.
Rev. 0.5, 03/03, page 125 of 438
Table 8.11 MD0 to MD3
Bit 3 1 MD3* 0 Bit 2 2 MD2* 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X X X Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
Legend X: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
Rev. 0.5, 03/03, page 126 of 438
8.3.3
Timer I/O Control Register (TIOR)
TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control A0 to A3 Specify the function of TGRA. Description I/O Control B0 to B3 Specify the function of TGRB.
TIORL_0, TIORL_3
Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control C0 to C3 Specify the function of TGRC. Description I/O Control D0 to D3 Specify the function of TGRD.
Rev. 0.5, 03/03, page 127 of 438
Table 8.12 TIORH_0 (Channel 0)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge Capture input source is TIOCB0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* Legend X: Don't care Note: * When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated.
Rev. 0.5, 03/03, page 128 of 438
Table 8.13 TIORL_0 (channel 0)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture 2 register* TGRD_0 Function Output compare 2 register* TIOCD0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge Capture input source is TIOCD0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down*
1
Legend X: Don't care Notes: 1. When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
Rev. 0.5, 03/03, page 129 of 438
Table 8.14 TIOR_1 (Channel 1)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges TGRC_0 compare match/ input capture Input capture at generation of TGRC_0 compare match/input capture Legend X: Don't care
Rev. 0.5, 03/03, page 130 of 438
Table 8.15 TIOR_2 (Channel 2)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend X: Don't care X Input capture register TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges
Rev. 0.5, 03/03, page 131 of 438
Table 8.16 TIORH_3 (Channel 3)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRB_3 Function Output compare register TIOCB3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCB3 pin Input capture at rising edge Capture input source is TIOCB3 pin Input capture at falling edge Capture input source is TIOCB3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* Legend X: Don't care Note: * When bits TPSC0 to TPSC2 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated.
Rev. 0.5, 03/03, page 132 of 438
Table 8.17 TIORL_3 (Channel 3)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture 2 register* TGRD_3 Function Output compare 2 register* TIOCD3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCD3 pin Input capture at rising edge Capture input source is TIOCD3 pin Input capture at falling edge Capture input source is TIOCD3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down*
1
Legend X: Don't care Notes: 1. When bits TPSC0 to TPSC2 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
Rev. 0.5, 03/03, page 133 of 438
Table 8.18 TIOR_4 (Channel 4)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRB_4 Function Output compare register TIOCB4 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCB4 pin Input capture at rising edge Capture input source is TIOCB4 pin Input capture at falling edge Capture input source is TIOCB4 pin Input capture at both edges Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture Legend X: Don't care
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Table 8.19 TIOR_5 (Channel 5)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend X: Don't care X Input capture register TGRB_5 Function Output compare register TIOCB5 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCB5 pin Input capture at rising edge Capture input source is TIOCB5 pin Input capture at falling edge Capture input source is TIOCB5 pin Input capture at both edges
Rev. 0.5, 03/03, page 135 of 438
Table 8.20 TIORH_0 (Channel 0)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* Legend X: Don't care Note: * When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated.
Rev. 0.5, 03/03, page 136 of 438
Table 8.21 TIORL_0 (Channel 0)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register* TGRC_0 Function Output compare register* TIOCC0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCC0 pin Input capture at rising edge Capture input source is TIOCC0 pin Input capture at falling edge Capture input source is TIOCC0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend X: Don't care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
Rev. 0.5, 03/03, page 137 of 438
Table 8.22 TIOR_1 (Channel 1)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge Capture input source is TIOCA1 pin Input capture at both edges Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture Legend X: Don't care
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Table 8.23 TIOR_2 (Channel 2)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend X: Don't care X Input capture register TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges
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Table 8.24 TIORH_3 (Channel 3)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRA_3 Function Output compare register TIOCA3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCA3 pin Input capture at rising edge Capture input source is TIOCA3 pin Input capture at falling edge Capture input source is TIOCA3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* Legend X: Don't care Note: * When bits TPSC0 to TPSC2 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated.
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Table 8.25 TIORL_3 (Channel 3)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture 2 register* TGRC_3 Function Output compare 2 register* TIOCC3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCC3 pin Input capture at rising edge Capture input source is TIOCC3 pin Input capture at falling edge Capture input source is TIOCC3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down*
1
Legend X: Don't care Notes: 1. When bits TPSC0 to TPSC2 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Table 8.26 TIOR_4 (Channel 4)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRA_4 Function Output compare register TIOCA4 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCA4 pin Input capture at rising edge Capture input source is TIOCA4 pin Input capture at falling edge Capture input source is TIOCA4 pin Input capture at both edges Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture Legend X: Don't care
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Table 8.27 TIOR_5 (Channel 5)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 Legend X: Don't care X Input capture register TGRA_5 Function Output compare register TIOCA5 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCA5 pin Input capture at rising edge Capture input source is TIOCA5 pin Input capture at falling edge Capture input source is TIOCA5 pin Input capture at both edges
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8.3.4
Timer Interrupt Enable Register (TIER)
TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel.
Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5 TCIEU 1 0 R/W Reserved This bit is always read as 1 and cannot be modified. Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled
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Bit 2
Bit Name TGIEC
Initial value 0
R/W R/W
Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled
8.3.5
Timer Status Register (TSR)
TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel.
Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 1 Reserved This bit is always read as 1 and cannot be modified.
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Bit 5
Bit Name TCFU
Initial value 0
R/W R/(W)*
Description Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1
4
TCFV
0
R/(W)*
Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1
3
TGFD
0
R/(W)*
Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register When 0 is written to TGFD after reading TGFD = 1
[Clearing condition] *
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Bit 2
Bit Name TGFC
Initial value 0
R/W R/(W)*
Description Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register When 0 is written to TGFC after reading TGFC = 1
[Clearing condition] * 1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register When 0 is written to TGFB after reading TGFB = 1
[Clearing condition] * 0 TGFA 0 R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] * * When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register When 0 is written to TGFA after reading TGFA = 1
[Clearing condition] * Note: * Only 0 can be written for clearing the flag.
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8.3.6
Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 8.3.7 Timer General Register (TGR)
The TGR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA-- TGRC and TGRB--TGRD. 8.3.8 Timer Start Register (TSTR)
TSTR selects the TCNT operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bit 7 6 5 4 3 2 1 0 Bit Name CST5 CST4 CST3 CST2 CST1 CST0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description Reserved Only 0 should be written to these bits. Counter Start 0 to 5 (CST0 to CST5) These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_0 to TCNT_5 count operation is stopped 1: TCNT_0 to TCNT_5 performs count operation
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8.3.9
Timer Synchro Register (TSYR)
TSYR selects independent operation or synchronous operation for channels 0 to 5 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit 7 6 5 4 3 2 1 0 Bit Name SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved Only 0 should be written to these bits. Timer Synchro 0 to 5 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_0 to TCNT_5 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_0 to TCNT_5 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible
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8.4
8.4.1
Operation
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of count operation setting procedure Figure 8.2 shows an example of the count operation setting procedure.
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation.
Operation selection
Select counter clock
[1]
Periodic counter
Free-running counter
Select counter clearing source
[2]
[3] Select output compare register
Set period
[4]
Start count operation
[5]
Start count operation
Figure 8.2 Example of Counter Operation Setting Procedure
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2. Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 8.3 illustrates free-running counter operation.
TCNT value H'FFFF
H'0000
Time
CST bit
TCFV
Figure 8.3 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 8.4 illustrates periodic counter operation.
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TCNT value TGR
Counter cleared by TGR compare match
H'0000
Time
CST bit Flag cleared by software initiation TGF
Figure 8.4 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of setting procedure for waveform output by compare match Figure 8.5 shows an example of the setting procedure for waveform output by compare match
[1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin unit the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation.
Output selection
Select waveform output mode
[1]
Set output timing
[2]
Start count operation
[3]

Figure 8.5 Example of Setting Procedure for Waveform Output by Compare Match
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2. Examples of waveform output operation Figure 8.6 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time
Figure 8.6 Example of 0 Output/1 Output Operation Figure 8.7 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output
TIOCB TIOCA
Figure 8.7 Example of Toggle Output Operation
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Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. 1. Example of input capture operation setting procedure Figure 8.8 shows an example of the input capture operation setting procedure.
[1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. [1]
Input selection
Select input capture input
Start count
[2]

Figure 8.8 Example of Input Capture Operation Setting Procedure
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2. Example of input capture operation Figure 8.9 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160
H'0010 H'0005 H'0000 Time
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB TGRB H'0180
Figure 8.9 Example of Input Capture Operation
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8.4.2
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 8.10 shows an example of the synchronous operation setting procedure.
Synchronous operation selection Set synchronous operation [1]
Synchronous presetting
Synchronous clearing
Set TCNT
[2]
Clearing source generation channel? Yes Select counter clearing source Start count
No
[3]
Set synchronous counter clearing Start count
[4]
[4]
[5]

[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 8.10 Example of Synchronous Operation Setting Procedure
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Example of Synchronous Operation: Figure 8.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting and synchronous clearing by TGRB_0 compare match are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 8.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time
TIOCA0 TIOCA1 TIOCA2
Figure 8.11 Example of Synchronous Operation 8.4.3 Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 8.28 shows the register combinations used in buffer operation.
Rev. 0.5, 03/03, page 157 of 438
Table 8.28 Register Combinations in Buffer Operation
Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3
* When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 8.12.
Compare match signal
Buffer register
Timer general register
Comparator
TCNT
Figure 8.12 Compare Match Buffer Operation * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 8.13.
Input capture signal
Buffer register
Timer general register
TCNT
Figure 8.13 Input Capture Buffer Operation
Rev. 0.5, 03/03, page 158 of 438
Example of Buffer Operation Setting Procedure: Figure 8.14 shows an example of the buffer operation setting procedure.
Buffer operation
Select TGR function
[1]
[1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation.
Set buffer operation
[2]
Start count
[3]

Figure 8.14 Example of Buffer Operation Setting Procedure Examples of Buffer Operation 1. When TGR is an output compare register Figure 8.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 8.4.5, PWM Modes.
Rev. 0.5, 03/03, page 159 of 438
TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520
H'0450
TIOCA
Figure 8.15 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 8.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value H'0F07 H'09FB H'0532 H'0000 Time
TIOCA
TGRA
H'0532
H'0F07
H'09FB
TGRC
H'0532
H'0F07
Figure 8.16 Example of Buffer Operation (2)
Rev. 0.5, 03/03, page 160 of 438
8.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 8.29 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 8.29 Cascaded Combinations
Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT_1 TCNT_4 Lower 16 Bits TCNT_2 TCNT_5
Example of Cascaded Operation Setting Procedure: Figure 8.17 shows an example of the setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
[1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation.
Start count
[2]

Figure 8.17 Cascaded Operation Setting Procedure Examples of Cascaded Operation: Figure 8.18 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1, when TGRA_1 and TGRA_2 have been designated as input capture registers, and when TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Rev. 0.5, 03/03, page 161 of 438
TCNT_1 clock TCNT_1 TCNT_2 clock TCNT_2 TIOCA1, TIOCA2 TGRA_1 H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2
TGRA_2
H'0000
Figure 8.18 Example of Cascaded Operation (1) Figure 8.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKA
TCLKB TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF
TCNT_1
0000
0001
0000
Figure 8.19 Example of Cascaded Operation (2) 8.4.5 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below.
Rev. 0.5, 03/03, page 162 of 438
* PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 8.30. Table 8.30 PWM Output Registers and Output Pins
Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGR4A_4 TGR4B_4 5 TGRA_5 TGRB_5 TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev. 0.5, 03/03, page 163 of 438
Example of PWM Mode Setting Procedure: Figure 8.20 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
[1]
Select counter clearing source
[2]
Select waveform output level
[3]
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 start the count operation.
Set TGR
[4]
Set PWM mode
[5]
Start count
[6]

Figure 8.20 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 8.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty levels.
TCNT value TGRA
Counter cleared by TGRA compare match
TGRB H'0000 Time
TIOCA
Figure 8.21 Example of PWM Mode Operation (1)
Rev. 0.5, 03/03, page 164 of 438
Figure 8.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels.
Counter cleared by TGRB_1 compare match
TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000
Time TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 8.22 Example of PWM Mode Operation (2)
Rev. 0.5, 03/03, page 165 of 438
Figure 8.23 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
TCNT value TGRB rewritten TGRA
TGRB H'0000
TGRB rewritten
TGRB rewritten Time
TIOCA
0% duty
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time
TIOCA
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten
TGRB H'0000 100% duty 0% duty
TGRB rewritten Time
TIOCA
Figure 8.23 Example of PWM Mode Operation (3)
Rev. 0.5, 03/03, page 166 of 438
8.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 8.31 shows the correspondence between external clock pins and channels. Table 8.31 Phase Counting Mode Clock Input Pins
External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 8.24 shows an example of the phase counting mode setting procedure.
Phase counting mode
[1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. [1]
Select phase counting mode
Start count
[2]

Figure 8.24 Example of Phase Counting Mode Setting Procedure
Rev. 0.5, 03/03, page 167 of 438
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 8.25 shows an example of phase counting mode 1 operation, and table 8.32 summarizes the TCNT up/down-count conditions.
TCLKA(channels 1 and 5) TCLKC(channels 2 and 4) TCLKB(channels 1 and 5) TCLKD(channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 8.25 Example of Phase Counting Mode 1 Operation Table 8.32 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count
Rev. 0.5, 03/03, page 168 of 438
2. Phase counting mode 2 Figure 8.26 shows an example of phase counting mode 2 operation, and table 8.33 summarizes the TCNT up/down-count conditions.
TCLKA(channels 1 and 5) TCLKC(channels 2 and 4) TCLKB(channels 1 and 5) TCLKD(channels 2 and 4) TCNT value Up-count Down-count
Time
Figure 8.26 Example of Phase Counting Mode 2 Operation Table 8.33 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count
Rev. 0.5, 03/03, page 169 of 438
3. Phase counting mode 3 Figure 8.27 shows an example of phase counting mode 3 operation, and table 8.34 summarizes the TCNT up/down-count conditions.
TCLKA(channels 1 and 5) TCLKC(channels 2 and 4) TCLKB(channels 1 and 5) TCLKD(channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 8.27 Example of Phase Counting Mode 3 Operation Table 8.34 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care
Rev. 0.5, 03/03, page 170 of 438
4. Phase counting mode 4 Figure 8.28 shows an example of phase counting mode 4 operation, and table 8.35 summarizes the TCNT up/down-count conditions.
TCLKA(channels 1 and 5) TCLKC(channels 2 and 4) TCLKB(channels 1 and 5) TCLKD(channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 8.28 Example of Phase Counting Mode 4 Operation Table 8.35 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count
Rev. 0.5, 03/03, page 171 of 438
Phase Counting Mode Application Example: Figure 8.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed.
Rev. 0.5, 03/03, page 172 of 438
Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1
TGRA_1 (speed period capture) TGRB_1 (speed period capture)
TCNT_0 + + -
TGRA_0 (speed control period) TGRC_0 (position control period)
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation) Channel 0
Figure 8.29 Phase Counting Mode Application Example
8.5
Interrupts
There are three kinds of TPU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 8.36 lists the TPU interrupt sources.
Rev. 0.5, 03/03, page 173 of 438
Table 8.36 TPU Interrupts
Channel 0 Name TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TCNT_4 overflow TCNT_4 underflow TGRA_5 input capture/compare match TGRB_5 input capture/compare match TCNT_5 overflow TCNT_5 underflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TCFV_4 TCFU_4 TGFA_5 TGFB_5 TCFV_5 TCFU_5
Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.
Rev. 0.5, 03/03, page 174 of 438
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5.
8.6
A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is begun. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.
Rev. 0.5, 03/03, page 175 of 438
8.7
8.7.1
Operation Timing
Input/Output Timing
TCNT Count Timing: Figure 8.30 shows TCNT count timing in internal clock operation, and figure 8.31 shows TCNT count timing in external clock operation.
Internal clock
Falling edge
Rising edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 8.30 Count Timing in Internal Clock Operation
External clock
Falling edge
Rising edge
Falling edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 8.31 Count Timing in External Clock Operation Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 8.32 shows output compare output timing.
Rev. 0.5, 03/03, page 176 of 438
TCNT input clock N N+1
TCNT
TGR
N
Compare match signal TIOC pin
Figure 8.32 Output Compare Output Timing Input Capture Signal Timing: Figure 8.33 shows input capture signal timing.
Input capture input Input capture signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 8.33 Input Capture Input Signal Timing
Rev. 0.5, 03/03, page 177 of 438
Timing for Counter Clearing by Compare Match/Input Capture: Figure 8.34 shows the timing when counter clearing on compare match is specified, and figure 8.35 shows the timing when counter clearing on input capture is specified.
Compare match signal Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 8.34 Counter Clear Timing (Compare Match)
Input capture signal
Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 8.35 Counter Clear Timing (Input Capture)
Rev. 0.5, 03/03, page 178 of 438
Buffer Operation Timing: Figures 8.36 and 8.37 show the timing in buffer operation.
TCNT
n
n+1
Compare match signal TGRA, TGRB TGRC, TGRD
n
N
N
Figure 8.36 Buffer Operation Timing (Compare Match)
Input capture signal
TCNT
N
N+1
TGRA, TGRB TGRC, TGRD
n
N
N+1
n
N
Figure 8.37 Buffer Operation Timing (Input Capture)
Rev. 0.5, 03/03, page 179 of 438
8.7.2
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 8.38 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
TCNT input clock
TCNT
N
N+1
TGR
N
Compare match signal
TGF flag
TGI interrupt
Figure 8.38 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 8.39 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
Input capture signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 8.39 TGI Interrupt Timing (Input Capture)
Rev. 0.5, 03/03, page 180 of 438
TCFV Flag/TCFU Flag Setting Timing: Figure 8.40 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 8.41 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing.
TCNT input clock TCNT (overflow) Overflow signal
H'FFFF
H'0000
TCFV flag
TCIV interrupt
Figure 8.40 TCIV Interrupt Setting Timing
TCNT input clock TCNT (underflow) Underflow signal
H'0000
H'FFFF
TCFU flag
TCIU interrupt
Figure 8.41 TCIU Interrupt Setting Timing
Rev. 0.5, 03/03, page 181 of 438
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 8.42 shows the timing for status flag clearing by the CPU.
TSR write cycle T1 T2
Address
TSR address
Write signal
Status flag
Interrupt request signal
Figure 8.42 Timing for Status Flag Clearing by CPU
Rev. 0.5, 03/03, page 182 of 438
8.8
8.8.1
Usage Notes
Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 16, Power-Down Modes. 8.8.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.43 shows the input clock conditions in phase counting mode.
Phase Phase differdifference Overlap ence
Overlap TCLKA (TCLKC) TCLKB (TCLKD)
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more
Figure 8.43 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 0.5, 03/03, page 183 of 438
8.8.3
Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where (N + 1) f : Counter frequency : Operating frequency N : TGR set value Contention between TCNT Write and Clear Operations
8.8.4
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 8.44 shows the timing in this case.
TCNT write cycle T1 T2
Address
TCNT address
Write signal Counter clear signal
TCNT
N
H'0000
Figure 8.44 Contention between TCNT Write and Clear Operations
Rev. 0.5, 03/03, page 184 of 438
8.8.5
Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 8.45 shows the timing in this case.
TCNT write cycle T1 T2
Address
TCNT address
Write signal TCNT input clock N TCNT write data M
TCNT
Figure 8.45 Contention between TCNT Write and Increment Operations 8.8.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the previous value is written. Figure 8.46 shows the timing in this case.
Rev. 0.5, 03/03, page 185 of 438
TGR write cycle T1 T2 Address TGR address
Write signal Compare match signal TCNT N N+1
Inhibited
TGR
N TGR write data
M
Figure 8.46 Contention between TGR Write and Compare Match 8.8.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation will be that in the buffer prior to the write. Figure 8.47 shows the timing in this case.
TGR write cycle T1 T2 Address Buffer register address
Write signal Compare match signal Buffer register write data Buffer register TGR N M
N
Figure 8.47 Contention between Buffer Register Write and Compare Match
Rev. 0.5, 03/03, page 186 of 438
8.8.8
Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 8.48 shows the timing in this case.
TGR read cycle T1 T2 Address TGR address
Read signal Input capture signal TGR X M
Internal data bus
M
Figure 8.48 Contention between TGR Read and Input Capture 8.8.9 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 8.49 shows the timing in this case.
Rev. 0.5, 03/03, page 187 of 438
TGR write cycle T1 T2 Address TGR address
Write signal Input capture signal TCNT M
TGR
M
Figure 8.49 Contention between TGR Write and Input Capture 8.8.10 Contention between Buffer Register Write and Input Capture
If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 8.50 shows the timing in this case.
Buffer register write cycle T1 T2 Address Buffer register address
Write signal Input capture signal TCNT N
TGR Buffer register
M
N
M
Figure 8.50 Contention between Buffer Register Write and Input Capture
Rev. 0.5, 03/03, page 188 of 438
8.8.11
Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 8.51 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR.
TCNT input clock TCNT Counter clear signal TGF Disabled TCFV H'FFFF H'0000
Figure 8.51 Contention between Overflow and Counter Clearing
Rev. 0.5, 03/03, page 189 of 438
8.8.12
Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 8.52 shows the operation timing when there is contention between TCNT write and overflow.
TCNT write cycle T1 T2
Address
TCNT address
Write signal
TCNT write data H'FFFF M
TCNT
TCFV flag
Figure 8.52 Contention between TCNT Write and Overflow 8.8.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 8.8.14 Interrupts in Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module stop mode.
Rev. 0.5, 03/03, page 190 of 438
Section 9 Watchdog Timer (WDT)
This LSI has a two-channel watchdog timer (WDT_0, WDT_1). WDT is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagrams of the WDT_0 and WDT_1 are shown in figures 9.1 and 9.2, respectively.
9.1
Features
* Selectable from eight counter input clocks (WDT_0) or sixteen counter input clocks (WDT_1) * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode * If the counter overflows, it is possible to select whether this LSI is internally reset or not or whether an internal NMI interrupt is generated or not. In interval timer mode * If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
WDT0100A_000020020200
Rev. 0.5, 03/03, page 191 of 438
Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select
Internal reset signal*
Reset control
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources
RSTCSR
TCNT_0
TCSR_0 Bus interface
Module bus WDT Legend TCSR_0 : Timer control/status register_0 TCNT_0 : Timer counter_0 RSTCSR : Reset control/status register Note: * An internal reset signal can be generated by setting the register.
Figure 9.1 Block Diagram of WDT_0
WOVI (interrupt request signal) Internal NMI interrupt request signal Internal reset signal*
Interrupt control Overflow Reset control Clock
Clock select
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock
SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256
TCNT_1
TCSR_1 Bus interface
Module bus WDT Legend TCSR_1 : Timer control/status register_1 TCNT_1 : Timer counter_1 Note: * An internal reset signal can be generated by setting the register.
Figure 9.2 Block Diagram of WDT_1
Rev. 0.5, 03/03, page 192 of 438
Internal bus
Internal bus
9.2
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different method to normal registers. For details, refer to section 9.5.1, Notes on Register Access. * Timer counter_0 (TCNT_0) * Timer control/status register_0 (TCSR_0) * Timer counter_1 (TCNT_1) * Timer control/status register_1 (TCSR_1) * Reset control/status register (RSTCSR) 9.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the TME bit in TCSR is cleared to 0. 9.2.2 Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT and the timer mode. * TCSR_0
Bit 7 Bit Name OVF Initial Value 0 R/W R/(W)* Description Overflow Flag Indicates that TCNT has overflowed. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode Rev. 0.5, 03/03, page 193 of 438
Bit 5
Bit Name TME
Initial Value 0
R/W R/W
Description Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.
4 3 2 1 0
-- -- CKS2 CKS1 CKS0
1 1 0 0 0
-- -- R/W R/W R/W
Reserved These bits are always read as 1 and cannot be modified. Clock Select 0 to 2 Selects the clock source to be input to TCNT. The overflow frequency for = 20 MHz is enclosed in parentheses. 000: Clock /2 (frequency: 25.6 s) 001: Clock /64 (frequency: 819.2 s) 010: Clock /128 (frequency: 1.6 ms) 011: Clock /512 (frequency: 6.6 ms) 100: Clock /2048 (frequency: 26.2 ms) 101: Clock /8192 (frequency: 104.9 ms) 110: Clock /32768 (frequency: 419.4 ms) 111: Clock /131072 (frequency: 1.68 s)
Note:
*
Only 0 can be written, for flag clearing.
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* TCSR_1
Bit 7 Bit Name OVF Initial Value 0 R/W R/(W)* Description Overflow Flag Indicates that TCNT has overflowed from H'FF to H'00. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided clock of -based prescaler (PSM) 1: Counts the divided clock of SUB-based prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects whether an internal reset request or an NMI interrupt request when the TCNT overflows during the watchdog timer mode. 0: NMI interrupt request 1: Internal reset request
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Bit 2 1 0
Bit Name CKS2 CKS1 CKS0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow cycle is the period from which TCNT starts incrementing at H00 and until it overflows. When PSS = 0 (values in parentheses are for = 20 MHz): 000: /2 (cycle: 25.6 s) 001: /64 (cycle: 819.2 ms) 010: /128 (cycle: 1.6 ms) 011: /512 (cycle: 6.6 ms) 100: /2048 (cycle: 26.2 ms) 101: /8192 (cycle: 104.9 ms) 110: /32768 (cycle: 419.4 ms) 111: /131072 (cycle: 1.68 s) When PSS = 1 (values in parentheses are for SUB = 32.768 kHz): 000: SUB/2 (cycle: 13.1 ms) 001: SUB/4 (cycle: 26.2 ms) 010: SUB/8 (cycle: 52.4 ms) 011: SUB/16 (cycle: 104.9 ms) 100: SUB/32 (cycle: 209.7 ms) 101: SUB/64 (cycle: 419.4 ms) 110: SUB/128 (cycle: 838.9 ms) 111: SUB/256 (cycle: 1.6777 s)
Note:
*
Only 0 can be written, for flag clearing.
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9.2.3
Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by overflows.
Bit 7 Bit Name WOVF Initial Value 0 R/W R/(W)* Description Watchdog Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, and then writing 0 to WOVF 6 RSTE 0 R/W Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 RSTS 0 R/W Reset Select Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. 0: Power-on reset 1: Setting prohibited 4 to 0 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. Note: * Only 0 can be written, for flag clearing.
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9.3
9.3.1
Operation
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. When the WDT is used as a watchdog timer, and if TCNT overflows without being rewritten because of a system malfunction or other error, a WDTOVF signal is output when using the WDT_0. In watchdog timer mode, the WDT can internally reset this LSI with a WDTOVF signal. When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal for this LSI is issued at the same time as a WDTOVF signal. In this case, select power-on reset by setting the RSTS bit in RSTCSR to 0. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The WDTOVF signal is output for 132 states when the RSTE bit = 1 in RSTCSR, and for 130 states when the RSTE bit = 0. The internal reset signal is output for 518 states. This is illustrated in figure 9.3 (a). When the TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If the RSTE bit in RSTCSR has been set to 1, an internal reset signal for the entire LSI is generated at TCNT overflow. In the case of the WDT_1, the chip is reset, or an NMI interrupt request is generated, for 516 system clock periods (516 ) (515 or 516 states when the clock source is SUB (PSS = 1)). This is illustrated in figure 9.3 (b). An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are both treated as having the same vector. So, avoid handling an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time.
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TCNT value Overflow H'FF
H'00 WT/ = 1 TME = 1 Write H'00 to TCNT WOVF = 1 Internal reset is generated
Internal reset signal* 2 518 states Legend WT/ : Timer mode select bit TME : Timer enable bit Notes: 1. After the WOVF bit becomes 1, it is cleared to 0 by an internal reset. 2. The internal reset signal is generated only if the RSTE bit is set to 1. *1
Time WT/ = 1 Write H'00 TME = 1 to TCNT
Figure 9.3 (a) WDT_0 Operation in Watchdog Timer Mode
TCNT value Overflow H'FF
H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT WOVF = 1*1 WT/IT = 1 TME = 1 Write H'00 to TCNT
Time
Internal reset is generated
Internal reset signal*
2
515/516 states Legend WT/IT : Timer mode select bit TME : Timer enable bit Notes: 1. After the WOVF bit becomes 1, it is cleared to 0 by an internal reset. 2. The internal reset signal is generated only if the RSTE bit is set to 1.
Figure 9.3 (b) WDT_1 Operation in Watchdog Timer Mode
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9.3.2
Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the time the OVF bit of the TCSR is set to 1.
9.4
Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. If an NMI interrupt request has been selected in watchdog timer mode, an NMI interrupt request is generated when the TCNT overflows. Table 9.1
Name WOVI NMI
WDT Interrupt Sources
Interrupt Source TCNT overflow (interval timer mode) TCNT overflow (watchdog timer mode) Interrupt Flag OVF OVF
9.5
9.5.1
Usage Notes
Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT, TCSR, and RSTCSR These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, the relative condition shown in figure 9.3 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer instruction cannot write to RSTCSR.
Rev. 0.5, 03/03, page 200 of 438
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, satisfy the condition shown in figure 9.4. If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, satisfy the condition shown in figure 9.4. If satisfied, the transfer instruction writes the values in bits 5 and 6 of the lower byte into the RSTE and RSTS bits, respectively, but has no effect on the WOVF bit.
TCNT write Writing to RSTE and RSTS bits Address: H'FF74 H'FF76 15 H'5A 8 7 Write data 0
TCSR write Writing 0 to WOVF bit Address: H'FF74 H'FF76 15 H'A5 8 7 0 Write data or H'00
Figure 9.4 Writing to TCNT, TCSR, and RSTCSR (example for WDT0) Reading TCNT, TCSR, and RSTCSR (WDT0) These registers are read in the same way as other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR. 9.5.2 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 9.5 shows this operation.
TCNT write cycle T1 T2 Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 9.5 Contention between TCNT Write and Increment
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9.5.3
Changing Value of CKS2 to CKS0
If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS0 to CKS2. 9.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 9.5.5 Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, however TCNT and TCSR of the WDT are reset. TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states after overflow to write 0 to the WOVF flag for clearing. 9.5.6 OVF Flag Clearing in Interval Timer Mode
When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0 to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before writing 0 to the OVF bit to clear the flag.
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Section 10 Serial Communication Interface (SCI)
This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Figure 10.1 shows a block diagram of the SCI.
10.1
Features
* Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source (except for in Smart Card interface mode). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Transmit-end, transmit-data-empty, receive-data-full, and receive error -- that can issue requests. * Module stop mode can be set Asynchronous mode * Data length: 7 or 8 bits * Stop bit length: 1 or 2 bits * Parity: Even, odd, or none * Receive error detection: Parity, overrun, and framing errors * Break detection: Break can be detected by reading the RxD pin level directly in the case of a framing error
SCI0000A_000020020200
Rev.0.5, 03/03, page 203 of 438
Clocked synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Smart Card interface * Automatic transmission of error signal (parity error) in receive mode * Error signal detection and automatic data retransmission in transmit mode * Direct convention and inverse convention both supported
Bus interface
Module data bus
Internal data bus
RDR
TDR
SCMR SSR SCR
BRR o Baud rate generator o/4 o/16 o/64 Clock
RxD
RSR
TSR
SMR
Transmission/ reception control
TxD
Parity generation Parity check
SCK
External clock TEI TXI RXI ERI
Legend RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register SCMR : Smart card mode register BRR : Bit rate register
Figure 10.1 Block Diagram of SCI
Rev. 0.5, 03/03, page 204 of 438
10.2
Input/Output Pins
Table 10.1 shows the serial pins for each SCI channel. Table 10.1 Pin Configuration
Channel 0 Pin Name* SCK0 RxD0 TxD0 1 SCK1 RxD1 TxD1 2 SCK2 RxD2 TxD2 Note: * I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation.
10.3
Register Descriptions
The SCI has the following registers for each channel. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions differ in part. * Receive Shift Register (RSR) * Receive Data Register (RDR) * Transmit Data Register (TDR) * Transmit Shift Register (TSR) * Serial Mode Register (SMR) * Serial Control Register (SCR) * Serial Status Register (SSR) * Smart Card Mode Register (SCMR) * Bit Rate Register (BRR)
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10.3.1
Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 10.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. 10.3.3 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. 10.3.4 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.
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10.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bit functions of SMR differ between normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF in SCMR is 0):
Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
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Bit 2
Bit Name MP
Initial Value 0
R/W R/W
Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode.
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select 0 and 1: These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 10.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 10.3.9, Bit Rate Register (BRR)).
Smart Card Interface Mode (When SMIF in SCMR is 1):
Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of one bit), and clock output control mode addition is performed. For details, refer to section 10.7.8, Clock Output Control. 6 BLK 0 R/W When this bit is set to 1, the SCI operates in block transfer mode. For details on block transfer mode, refer to section 10.7.3, Block Transfer Mode. Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data in transmission, and the parity bit is checked in reception. In Smart Card interface mode, this bit must be set to 1.
5
PE
0
R/W
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Bit 4
Bit Name O/E
Initial Value 0
R/W R/W
Description Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. For details on setting this bit in Smart Card interface mode, refer to section 10.7.2, Data Format (Except for Block Transfer Mode).
3 2
BCP1 BCP0
0 0
R/W R/W
Basic Clock Pulse 1 and 2 These bits specify the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. 00: 32 clock (S = 32) 01: 64 clock (S = 64) 10: 372 clock (S = 372) 11: 256 clock (S = 256) For details, refer to section 10.7.4, Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode. S stands for the value of S in BRR (see section 10.3.9, Bit Rate Register (BRR)).
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select 0 and 1 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 10.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 10.3.9, Bit Rate Register (BRR)).
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10.3.6
Serial Control Register (SCR)
SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also used to selection of the transfer clock source. For details on interrupt requests, refer to section 10.8, Interrupt Sources. Some bit functions of SCR differ between normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF in SCMR is 0):
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit s set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 10.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable This bit is set to 1, TEI interrupt request is enabled.
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Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 0 and 1 Selects the clock source and SCK pin function. Asynchronous mode 00: Internal clock SCK pin functions as I/O port 01: Internal clock Outputs a clock of the same frequency as the bit rate from the SCK pin. 1X: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK pin. Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output) 1X: External clock (SCK pin functions as clock input)
Legend X: Don't care
Smart Card Interface Mode (When SMIF in SCMR is 1):
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode. 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode.
Rev.0.5, 03/03, page 211 of 438
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W
Description Clock Enable 0 and 1 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 10.7.8, Clock Output Control. When the GM bit in SMR is 0: 00: Output disabled (SCK pin can be used as an I/O port pin) 01: Clock output 1X: Reserved When the GM bit in SMR is 1: 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output
Legend X: Don't care
10.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ between normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF in SCMR is 0):
Bit 7 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR When 0 is written to TDRE after reading TDRE = 1
[Clearing condition] *
Rev. 0.5, 03/03, page 212 of 438
Bit 6
Bit Name RDRF
Initial Value 0
R/W R/W
Description Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1
[Clearing condition] *
The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 5 ORER 0 R/W Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to ORER after reading ORER = 1
[Clearing condition] * 4 FER 0 R/W
Framing Error [Setting condition] * * When the stop bit is 0 When 0 is written to FER after reading FER = 1 [Clearing condition] In 2-stop-bit mode, only the first stop bit is checked.
3
PER
0
R/W
Parity Error [Setting condition] * * When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition]
Rev.0.5, 03/03, page 213 of 438
Bit 2
Bit Name TEND
Initial Value 1
R/W R
Description Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after reading TDRE = 1
[Clearing condition] * 1 MPB 0 R
Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit data.
Smart Card Interface Mode (When SMIF in SCMR is 1):
Bit 7 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR When 0 is written to TDRE after reading TDRE = 1
[Clearing condition] *
Rev. 0.5, 03/03, page 214 of 438
Bit 6
Bit Name RDRF
Initial Value 0
R/W R/W
Description Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1
[Clearing condition] *
The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 5 ORER 0 R/W Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to ORER after reading ORER = 1
[Clearing condition] * 4 ERS 0 R/W
Error Signal Status [Setting condition] * * When the low level of the error signal is sampled When 0 is written to ERS after reading ERS = 1 [Clearing condition]
3
PER
0
R/W
Parity Error [Setting condition] * * When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition]
Rev.0.5, 03/03, page 215 of 438
Bit 2
Bit Name TEND
Initial Value 1
R/W R
Description Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When the TE bit in SCR is 0 and the ERS bit is also 0 When the ESR bit is 0 and the TDRE bit is 1 after the specified interval following transmission of 1byte data.
The timing of bit setting differs according to the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission starts When GM = 0 and BLK = 1, 1.5 etu after transmission starts When GM = 1 and BLK = 0, 1.0 etu after transmission starts When GM = 1 and BLK = 1, 1.0 etu after transmission starts [Clearing condition] * 1 0 MPB MPBT 0 0 R R/W When 0 is written to TDRE after reading TDRE = 1
Multiprocessor Bit This bit is not used in Smart Card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in Smart Card interface mode.
Rev. 0.5, 03/03, page 216 of 438
10.3.8
Smart Card Mode Register (SCMR)
SCMR is a register that selects Smart Card interface mode and its format.
Bit 7 to 4 3 Bit Name SDIR Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits. For 7-bit data, LSB-first is fixed. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR 1 0 SMIF 1 0 R/W Reserved This bit is always read as 1. Smart Card Interface Mode Select This bit is set to 1 to make the SCI operate in Smart Card interface mode. 0: Normal asynchronous mode or clocked synchronous mode 1: Smart card interface mode
Rev.0.5, 03/03, page 217 of 438
10.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 10.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Table 10.2 Relationships between N Setting in BRR and Bit Rate B
Mode Asynchronous Mode Clocked Synchronous Mode Smart Card Interface Mode Bit Rate Error
B=
64 8 2
2n-1
106 (N + 1)
2 2n-1
Error (%) = {
B 64
106 (N + 1)
2 2n-1
-1 }
100
B=
106 (N + 1) 106 (N + 1) Error (%) = { B S 106 (N + 1) -1 } 100
B=
S 2 2n-1
2 2n-1
Note: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following tables. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 BCP1 0 0 1 1 SMR Setting BCP0 0 1 0 1 S 32 64 372 256
Table 10.3 shows sample N settings in BRR in normal asynchronous mode. Table 10.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 10.6 shows sample N settings in BRR in clocked synchronous mode. Table 10.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in a 1-bit transfer interval) can be selected. For details, refer to section 10.7.4, Receive Data Sampling Timing and Reception Margin. Tables 10.5 and 10.7 show the maximum bit rates with external clock input.
Rev. 0.5, 03/03, page 218 of 438
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 4 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 4.9152 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73
Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 -- 0 7.3728 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 --
Rev.0.5, 03/03, page 219 of 438
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
Operating Frequency (MHz) 14 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- Error (%) -0.17 0.13 0.13 0.13 0.13 0.13 0.13 -0.93 -0.93 0.00 -- n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.00 0.13 n 3 2 2 1 1 0 0 0 0 0 0 17.2032 N 75 223 111 223 111 223 111 55 27 13 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00
Rev. 0.5, 03/03, page 220 of 438
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 24 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34
Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
(MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 n 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 (MHz) 12.288 14 14.7456 16 17.2032 18 19.6608 20 24 Maximum Bit Rate (bit/s) 384000 437500 460800 500000 537600 562500 614400 625000 750000 n 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0
Rev.0.5, 03/03, page 221 of 438
Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
(MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 External Input Clock (MHz) 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 Maximum Bit Rate (bit/s) 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 (MHz) 12.288 14 14.7456 16 17.2032 18 19.6608 20 24 External Input Clock (MHz) 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 6.0000 Maximum Bit Rate (bit/s) 192000 218750 230400 250000 268800 281250 307200 312500 375000
Rev. 0.5, 03/03, page 222 of 438
Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M Legend Blank : Cannot be set. -- : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. 4 n -- 2 2 1 1 0 0 0 0 0 0 0 0 N -- 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* -- -- 2 2 1 1 1 0 0 0 0 -- -- -- -- 149 74 149 59 29 59 23 11 5 -- -- n 8 N n 10 N n 16 N n 20 N n 24 N
Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
(MHz) 4 6 8 10 12 External Input Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 Maximum Bit Rate (bit/s) 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 (MHz) 14 16 18 20 24 External Input Clock (MHz) 2.3333 2.6667 3.0000 3.3333 4.0000 Maximum Bit Rate (bit/s) 2333333.3 2666666.7 3000000.0 3333333.3 4000000.0
Rev.0.5, 03/03, page 223 of 438
Table 10.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372)
Operating Frequency (MHz) 7.1424 Bit Rate (bit/s) 9600 n 0 N 0 Error (%) 0.00 n 0 10.00 N 1 Error (%) 30 n 0 10.7136 N 1 Error (%) 25 n 0 13.00 N 1 Error (%) 8.99
Operating Frequency (MHz) 14.2848 Bit Rate (bit/s) 9600 n 0 N 1 Error (%) 0.00 n 0 16.00 N 1 Error (%) n 18.00 N 2 Error (%) 15.99 n 0 20.00 N 2 Error (%) 6.60 n 0 24.00 N 2 Error (%) 12.01
12.01 0
Table 10.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372)
(MHz) 7.1424 10.00 10.7136 13.00 14.2848 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 n 0 0 0 0 0 N 0 0 0 0 0 (MHz) 16.00 18.00 20.00 24.00 Maximum Bit Rate (bit/s) 21505 24194 26882 32258 n 0 0 0 0 N 0 0 0 0
Rev. 0.5, 03/03, page 224 of 438
10.4
Operation in Asynchronous Mode
Figure 10.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line. When the transmission line goes to the space state (low level), the SCI recognizes a start bit and starts serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
Idle state (mark state) 1 0/1 Parity bit 1 bit, or none 1 1
1 Serial data 0 Start bit 1 bit
LSB D0 D1 D2 D3 D4 D5 D6
MSB D7
Stop bit
Transmit/receive data 7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 10.4.1 Data Transfer Format
Table 10.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 10.5, Multiprocessor Communication Function.
Rev.0.5, 03/03, page 225 of 438
Table 10.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10
STOP
11
12
S S S S S S S S S S S S
8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data
STOP
STOP STOP
P STOP
P STOP STOP
STOP STOP
P
STOP
P
STOP STOP
MPB STOP
MPB STOP STOP
MPB STOP
MPB STOP STOP
Legend S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit
Rev. 0.5, 03/03, page 226 of 438
10.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 10.3. Thus, the reception margin in asynchronous mode is given by formula (1) below.
M = { (0.5 - D - 0.5 1 )- N 2N - (L - 0.5) F} 100 [%]
... Formula (1) Where M N D L F : Reception margin : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0.5 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
16 clocks 8 clocks 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0
Start bit
D0
D1
Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode
Rev.0.5, 03/03, page 227 of 438
10.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 10.4.
SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 10.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)
Rev. 0.5, 03/03, page 228 of 438
10.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
[4]
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE, RE bits 0)
[1]
Set data transfer format in SMR and SCMR Set value in BRR Wait
[2]
[3]
No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits

Figure 10.5 Sample SCI Initialization Flowchart
Rev.0.5, 03/03, page 229 of 438
10.4.5
Data Transmission (Asynchronous Mode)
Figure 10.6 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 10.7 shows a sample flowchart for transmission in asynchronous mode.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1
1
1 Idle state (mark state)
TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt service routine
TEI interrupt request generated
1 frame
Figure 10.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 0.5, 03/03, page 230 of 438
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure:
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3] Read TEND flag in SSR
To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0.
No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1
[4]
Clear TE bit in SCR to 0
Figure 10.7 Sample Serial Transmission Flowchart
Rev.0.5, 03/03, page 231 of 438
10.4.6
Serial Data Reception (Asynchronous Mode)
Figure 10.8 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0
1
1 Idle state (mark state)
RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ERI interrupt request generated by framing error
1 frame
Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 0.5, 03/03, page 232 of 438
Table 10.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.9 shows a sample flow chart for serial data reception. Table 10.11 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception.
Rev.0.5, 03/03, page 233 of 438
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
[2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin.
Read ORER, PER, and FER flags in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
[4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0.
No All data received? Yes Clear RE bit in SCR to 0 [5]
Figure 10.9 Sample Serial Reception Data Flowchart (1)
Rev. 0.5, 03/03, page 234 of 438
[3] Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
No PER = 1 Yes Parity error processing
Clear ORER, PER, and FER flags in SSR to 0

Figure 10.9 Sample Serial Reception Data Flowchart (2)
Rev.0.5, 03/03, page 235 of 438
10.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 10.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
Rev. 0.5, 03/03, page 236 of 438
Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04)
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID Legend MPB: Multiprocessor bit
Figure 10.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
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10.5.1
Multiprocessor Serial Data Transmission
Figure 10.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure:
No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR
Clear TDRE flag to 0
No All data transmitted? Yes [3]
To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to 1, clear DR to 0, then clear the TE bit in SCR to 0.
Read TEND flag in SSR
No TEND = 1 Yes No Break output? Yes [4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0

Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart
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10.5.2
Multiprocessor Serial Data Reception
Figure 10.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 10.12 shows an example of SCI operation for multiprocessor format reception.
Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data1) D1 D7 Stop MPB bit 0
1
1
1 Idle state (mark state)
MPIE
RDRF
RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state
(a) Data does not match station's ID
1
Start bit 0 D0 D1
Data (ID2) D7
Stop MPB bit 1 1
Start bit 0 D0
Data (Data2) D1 D7
Stop MPB bit 0
1
1 Idle state (mark state)
MPIE
RDRF
RDR value
ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine
Data2 MPIE bit set to 1 again
(b) Data matches station's ID
Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev.0.5, 03/03, page 239 of 438
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value.
Read MPIE bit in SCR Read ORER and FER flags in SSR
[2]
Yes FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [3]
[5] Error processing (Continued on next page)
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 0.5, 03/03, page 240 of 438
[5]
Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
Clear ORER and FER flags in SSR to 0

Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2)
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10.6
Operation in Clocked Synchronous Mode
Figure 10.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 10.14 Data Format in Synchronous Communication (For LSB-First) 10.6.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE0 and CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high.
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10.6.2
SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the SCI should be initialized as described in a sample flowchart in figure 10.15. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Start initialization
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR.
[1]
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE, RE bits 0)
[3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
Set data transfer format in SMR and SCMR Set value in BRR Wait
[2]
[3]
No 1-bit interval elapsed? Yes
Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits
[4]

Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously.
Figure 10.15 Sample SCI Initialization Flowchart
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10.6.3
Serial Data Transmission (Clocked Synchronous Mode)
Figure 10.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has been completed. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 10.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags.
Rev. 0.5, 03/03, page 244 of 438
Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Rev.0.5, 03/03, page 245 of 438
Initialization Start transmission
[1]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0.
Read TDRE flag in SSR
[2]
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3]
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR to 0
Figure 10.17 Sample Serial Transmission Flowchart
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10.6.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 10.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished.
Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 10.18 Example of SCI Operation in Reception Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.19 shows a sample flow chart for serial data reception.
Rev.0.5, 03/03, page 247 of 438
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished.
Read ORER flag in SSR
[2]
Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR [4]
No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
No All data received? Yes Clear RE bit in SCR to 0 [5]
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
Figure 10.19 Sample Serial Reception Flowchart
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10.6.5
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
Figure 10.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Rev.0.5, 03/03, page 249 of 438
Initialization Start transmission/reception
[1]
[1]
SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0.
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
[2]
[2]
[3]
Read ORER flag in SSR Yes [3] Error processing
ORER = 1 No
[4]
Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
[4]
[5]
No All data received? Yes [5]
Clear TE and RE bits in SCR to 0
Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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10.7
Operation in Smart Card Interface
The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface mode is carried out by means of a register setting. 10.7.1 Pin Connection Example
Figure 10.21 shows an example of connection with the Smart Card. In communication with an IC card, as both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal.
VCC TxD RxD SCK Rx (port) This LSI Connected equipment Data line Clock line Reset line I/O CLK RST IC card
Figure 10.21 Schematic Diagram of Smart Card Interface Pin Connections
Rev.0.5, 03/03, page 251 of 438
10.7.2
Data Format (Except for Block Transfer Mode)
Figure 10.22 shows the transfer data format in Smart Card interface mode. * One frame consists of 8-bit data plus a parity bit in asynchronous mode. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If an error signal is sampled during transmission, the same data is retransmitted automatically after a delay of 2 etu or longer.
When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitting station output
When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Transmitting station output Receiving station output
Legend : Start bit DS D0 to D7 : Data bits : Parity bit Dp : Error signal DE
Figure 10.22 Normal Smart Card Interface Data Format Data transfer with other types of IC cards (direct convention and inverse convention) are performed as described in the following.
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State
Figure 10.23 Direct Convention (SDIR = SINV = O/E = 0) E
Rev. 0.5, 03/03, page 252 of 438
With the direction convention type IC and the above sample start character, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode.
(Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State
E Figure 10.24 Inverse Convention (SDIR = SINV = O/E = 1) With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data for the above is H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception. 10.7.3 Block Transfer Mode
Operation in block transfer mode is the same as that in SCI asynchronous mode, except for the following points. * In reception, though the parity check is performed, no error signal is output even if an error is detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the parity bit of the next frame. * In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. * In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu after transmission start. * As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transfer is not performed, this flag is always cleared to 0.
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10.7.4
Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode
In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 10.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula.
M = | (0.5 - | D - 0.5 | 1 ) - (L - 0.5) F - (1 + F) | N 2N 100%
Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. M = (0.5 - 1/2 x 372) x 100% = 49.866%
372 clocks 186 clocks 0 Internal basic clock 185 371 0 185 371 0
Receive data (RxD) Synchronization sampling timing
Start bit
D0
D1
Data sampling timing
Figure 10.25 Receive Data Sampling Timing in Smart Card Interface Mode (Using Clock of 372 Times the Transfer Rate)
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10.7.5
Initialization
Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP0, BCP1, CKS0, CKS1 bits in SMR. Set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. To switch from receive mode to transmit mode, after checking that the SCI has finished reception, initialize the SCI, and set RE to 0 and TE to 1. Whether SCI has finished reception or not can be checked with the RDRF, PER, or ORER flags. To switch from transmit mode to receive mode, after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to 1. Whether SCI has finished transmission or not can be checked with the TEND flag. 10.7.6 Data Transmission (Except for Block Transfer Mode)
As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 10.26 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving end after transmission of one frame is complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. 2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality is received. Data is retransferred from TDR to TSR, and retransmitted automatically. 3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. Transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. Writing transmit data to TDR transfers the next transmit data.
Rev.0.5, 03/03, page 255 of 438
Figure 10.28 shows a flowchart for transmission. In the event of an error in transmission, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0. Therefore, the SCI will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared.
Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4
nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6]
Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer to TSR from TDR
Transfer to TSR from TDR [9]
[8]
Figure 10.26 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 10.27.
I/O data TXI (TEND interrupt) When GM = 0
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE Guard time
12.5etu
11.0etu When GM = 1
Legend Ds D0 to D7 Dp DE
: Start bit : Data bits : Parity bit : Error signal
Figure 10.27 TEND Flag Generation Timing in Transmission Operation
Rev. 0.5, 03/03, page 256 of 438
Start
Initialization Start transmission
ERS = 0? Yes
No
Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0
No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0
End
Figure 10.28 Example of Transmission Processing Flow
Rev.0.5, 03/03, page 257 of 438
10.7.7
Serial Data Reception (Except for Block Transfer Mode)
Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 10.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. 2. The RDRF bit in SSR is not set for a frame in which an error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. Figure 10.30 shows a flowchart for reception. If an error occurs in receive mode and the ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. Hence, so the error flag must be cleared to 0. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been received is transferred to RDR and can be read from there. Note: For details on receive operations in block transfer mode, refer to section 10.4, Operation in Asynchronous Mode.
Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4
nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1]
Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
[4]
[3]
Figure 10.29 Retransfer Operation in SCI Receive Mode
Rev. 0.5, 03/03, page 258 of 438
Start
Initialization
Start reception
ORER = 0 and PER = 0 Yes
No
Error processing No
RDRF = 1? Yes
Read RDR and clear RDRF flag in SSR to 0
No
All data received? Yes Clear RE bit to 0
Figure 10.30 Example of Reception Processing Flow 10.7.8 Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 10.31 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 10.31 Timing for Fixing Clock Output Level
Rev.0.5, 03/03, page 259 of 438
When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. Powering On: To secure clock duty from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to smart card mode operation. 4. Set the CKE0 bit in SCR to 1 to start clock output. When changing from smart card interface mode to software standby mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to halt the clock. 4. Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. 5. Make the transition to the software standby state. When returning to smart card interface mode from software standby mode: 1. Exit the software standby state. 2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty.
Software standby
Normal operation
Normal operation
[1] [2] [3]
[4] [5]
[6] [7]
Figure 10.32 Clock Halt and Restart Procedure
Rev. 0.5, 03/03, page 260 of 438
10.8
10.8.1
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode
Table 10.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 10.12 SCI Interrupt Sources
Channel 0 Name ERI0 RXI0 TXI0 TEI0 1 ERI1 RXI1 TXI1 TEI1 2 ERI2 RXI2 TXI2 TEI2 Interrupt Source Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND
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10.8.2
Interrupts in Smart Card Interface Mode
Table 10.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 10.13 SCI Interrupt Sources
Channel 0 Name ERI0 RXI0 TXI0 1 ERI1 RXI1 TXI1 2 ERI2 RXI2 TXI2 Interrupt Source Receive Error, detection Receive Data Full Transmit Data Empty Receive Error, detection Receive Data Full Transmit Data Empty Receive Error, detection Receive Data Full Transmit Data Empty Interrupt Flag ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND
In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR is set, and a TXI interrupt is generated. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0. Therefore, the SCI will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs. Hence, the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared.
Rev. 0.5, 03/03, page 262 of 438
10.9
10.9.1
Usage Notes
Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 16, Power-Down Modes. 10.9.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 10.9.3 Mark State and Break Detection
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 10.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
Rev.0.5, 03/03, page 263 of 438
Rev. 0.5, 03/03, page 264 of 438
Section 11 Hitachi Controller Area Network (HCAN)
The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. For details on CAN specification, refer to Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH. The block diagram of the HCAN is shown in figure 11.1.
11.1
Features
* CAN version: Bosch 2.0B active compatible Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function) Broadcast communication system Transmission path: Bidirectional 2-wire serial communication Communication speed: Max. 1 Mbps Data length: 0 to 8 bytes * Number of channels: 1 * Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception) * Data transmission: Two methods Mailbox (buffer) number order (low-to-high) Message priority (identifier) reverse-order (high-to-low) * Data reception: Two methods Message identifier match (transmit/receive-setting buffers) Reception with message identifier masked (receive-only) * CPU interrupts: 12 Error interrupt Reset processing interrupt Message reception interrupt Message transmission interrupt * HCAN operating modes * Support for various modes Hardware reset Software reset Normal status (error-active, error-passive) Bus off status HCAN configuration mode HCAN sleep mode HCAN halt mode
IFCAN00B_000120020200
Rev. 0.5, 03/03, page 265 of 438
* Module stop mode can be set
HCAN
Peripheral address bus
Peripheral data bus
MBI Message buffer Mailboxes Message control Message data MC0-MC15, MD0-MD15
LAFM
(CDLC) CAN Data Link Controller Bosch CAN 2.0B active HTxD
Tx buffer
MPI Microprocessor interface CPU interface Control register Status register
Rx buffer
HRxD
Figure 11.1 HCAN Block Diagram * Message Buffer Interface (MBI) The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU. For receive messages, the data received by the CDLC is stored automatically. * Microprocessor Interface (MPI) The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, status, and so forth. * CAN Data Link Controller (CDLC) The CDLC transmits and receives of messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as well as CRC checking, bus arbitration, and other functions.
Rev. 0.5, 03/03, page 266 of 438
11.2
Input/Output Pins
Table 11.1 shows the HCAN's pins. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 11.1 Pin Configuration
Name HCAN transmit data pin HCAN receive data pin Abbreviation HTxD HRxD Input/Output Output Input Function CAN bus transmission pin CAN bus reception pin
A bus driver is necessary for the interface between the pins and the CAN bus. A Philips PCA82C250 compatible model is recommended.
11.3
Register Descriptions
The HCAN has the following registers. * Master control register (MCR) * General status register (GSR) * Bit configuration register (BCR) * Mailbox configuration register (MBCR) * Transmit wait register (TXPR) * Transmit wait cancel register (TXCR) * Transmit acknowledge register (TXACK) * Abort acknowledge register (ABACK) * Receive complete register (RXPR) * Remote request register (RFPR) * Interrupt register (IRR) * Mailbox interrupt mask register (MBIMR) * Interrupt mask register (IMR) * Receive error counter (REC) * Transmit error counter (TEC) * Unread message status register (UMSR) * Local acceptance filter mask H (LAFMH) * Local acceptance filter mask L (LAFML) * Message control (8-bit x 8 registers x 16 sets) (MC0 to MC15) * Message data (8-bit x 8 registers x 16 sets) (MD0 to MD15)
Rev. 0.5, 03/03, page 267 of 438
* HCAN monitor register (HCANMON) 11.3.1 Master Control Register (MCR)
MCR controls the HCAN.
Bit 7 Bit Name MCR7 Initial Value 0 R/W R/W Description HCAN Sleep Mode Release When this bit is set to 1, the HCAN automatically exits HCAN sleep mode on detection of CAN bus operation. 6 0 R Reserved This bit is always read as 0. Only 0 should be written to this bit. 5 MCR5 0 R/W HCAN Sleep Mode When this bit is set to 1, the HCAN transits to HCAN sleep mode. When this bit is cleared to 0, HCAN sleep mode is released. 4 3 2 MCR2 0 0 0 R R R/W Reserved These bits are always read as 0. Only 0 should be written to these bits. Message Transmission Method 0: Transmission order determined by message identifier priority 1: Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) 1 MCR1 0 R/W Halt Request When this bit is set to 1, the HCAN transits to HCAN HALT mode. When this bit is cleared to 0, HCAN HALT mode is released.
Rev. 0.5, 03/03, page 268 of 438
Bit 0
Bit Name MCR0
Initial Value 1
R/W R/W
Description Reset Request When this bit is set to 1, the HCAN transits to reset mode. For details, refer to section 11.4.1, Hardware and Software Resets. [Setting conditions] * * * * * Power-on reset Hardware standby Software standby 1-write (software reset) When 0 is written to this bit while the GSR3 bit in GSR is 1
[Clearing condition]
11.3.2
General Status Register (GSR)
GSR indicates the status of the HCAN.
Bit 7 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. Only 0 should be written to these bits. 3 GSR3 1 R Reset Status Bit Indicates whether the HCAN module is in the normal operating state or the reset state. This bit cannot be modified. [Setting condition] * * * When entering configuration mode after the HCAN internal reset has finished Sleep mode When entering normal operation mode after the MCR0 bit in MCR is cleared to 0 (Note that there is a delay between clearing of the MCR0 bit and the GSR3 bit.)
[Clearing condition]
Rev. 0.5, 03/03, page 269 of 438
Bit 2
Bit Name GSR2
Initial Value 1
R/W R
Description Message Transmission Status Flag Flag that indicates whether the module is currently in the message transmission period. This bit cannot be modified. [Setting condition] * * Start of message transmission (SOF) Interval of three bits after EOF (End of Frame) [Clearing condition]
1
GSR1
0
R
Transmit/Receive Warning Flag This bit cannot be modified. [Clearing condition] * * When TEC < 96 and REC < 96 or TEC 256 When TEC 96 or REC 96 [Setting condition]
0
GSR0
0
R
Bus Off Flag This bit cannot be modified. [Setting condition] * * When TEC 256 (bus off state) Recovery from bus off state [Clearing condition]
Rev. 0.5, 03/03, page 270 of 438
11.3.3
Bit Configuration Register (BCR)
BCR sets HCAN bit timing parameters and the baud rate prescaler. For details on parameters, refer to section 11.4.2, Initialization after Hardware Reset.
Bit 15 14 Bit Name BCR7 BCR6 Initial Value 0 0 R/W R/W R/W Description Re-Synchronization Jump Width (SJW) Set the maximum bit synchronization width. 00: 1 time quantum 01: 2 time quanta 10: 3 time quanta 11: 4 time quanta 13 12 11 10 9 8 7 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 BCR15 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Baud Rate Prescaler (BRP) Set the length of time quantum. 000000: 2 x system clock 000001: 4 x system clock 000010: 6 x system clock : 111111: 128 x system clock Bit Sample Point (BSP) Sets the point at which data is sampled. 0: Bit sampling at one point (end of time segment 1 (TSEG1)) 1: Bit sampling at three points (end of TSEG1 and preceding and following one time quantum) 6 5 4 BCR14 BCR13 BCR12 0 0 0 R/W R/W R/W Time Segment 2 (TSEG2) Set the TSEG2 width within a range of 2 to 8 time quanta. 000: Setting prohibited 001: 2 time quanta 010: 3 time quanta 011: 4 time quanta 100: 5 time quanta 101: 6 time quanta 110: 7 time quanta 111: 8 time quanta
Rev. 0.5, 03/03, page 271 of 438
Bit 3 2 1 0
Bit Name BCR11 BCR10 BCR9 BCR8
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description Time Segment 1 (TSEG1) Set the TSEG1 (PRSEG + PHSEG1) width to between 4 and 16 time quanta. 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: 4 time quanta 0100: 5 time quanta 0101: 6 time quanta 0110: 7 time quanta 0111: 8 time quanta 1000: 9 time quanta 1001: 10 time quanta 1010: 11 time quanta 1011: 12 time quanta 1100: 13 time quanta 1101: 14 time quanta 1110: 15 time quanta 1111: 16 time quanta
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11.3.4
Mailbox Configuration Register (MBCR)
MBCR sets the transfer direction for each mailbox.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 Initial Value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Description These bits set the transfer direction for the corresponding mailboxes from 1 to 15. MBCRn determines the transfer direction for mailbox n (n =1 to 15). 0: Corresponding mailbox is set for transmission 1: Corresponding mailbox is set for reception Bit 8 is reserved. This bit is always read as 1 and the write value should always be 1.
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11.3.5
Transmit Wait Register (TXPR)
TXPR sets a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait).
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Description These bits set a transmit wait (CAN bus arbitration wait) for the corresponding mailboxes 1 to 15. When TXPRn (n = 1 to 15) is set to 1, the message in mailbox n becomes the transmit wait state. [Clearing condition] * * Completion of message transmission Completion of transmission cancellation
Bit 8 is reserved. This bit is always read as 1 and the write value should always be 1.
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11.3.6
Transmit Wait Cancel Register (TXCR)
TXCR controls canceling transmission of transmit wait messages in mailboxes (buffers).
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Description These bits cancel the transmit wait message in the corresponding mailboxes 1 to 15. When TXCRn (n = 1 to 15) is set to 1, the transmit wait message in mailbox n is canceled. [Clearing condition] * Completion of TXPR clearing when transmit message is canceled normally
Bit 8 is reserved. This bit is always read as 0 and the write value should always be 0.
Rev. 0.5, 03/03, page 275 of 438
11.3.7
Transmit Acknowledge Register (TXACK)
TXACK is a status register that indicates the normal transmission of mailbox (buffer) transmit messages.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W * Description These bits are status flags that indicate error-free transmission of the transmit message in the corresponding mailboxes 1 to 15. When the message in mailbox n (n = 1 to 15) has been transmitted errorfree, TXACKn is set to 1. [Setting condition] * Completion of message transmission for corresponding mailbox Writing 1
[Clearing condition] Bit 8 is reserved. This bit is always read as 0 and the write value should always be 0.
Rev. 0.5, 03/03, page 276 of 438
11.3.8
Abort Acknowledge Register (ABACK)
ABACK is a status register that indicates the normal cancellation (aborting) of mailbox (buffer) transmit messages.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* * Description These bits are status flags that indicate error-free cancellation (abortion) of the transmit message in the corresponding mailboxes 1 to 15. When the message in mailbox n (n = 1 to 15) has been canceled errorfree, ABACKn is set to 1. [Setting condition] * Completion of transmit message cancellation for corresponding mailbox Writing 1
[Clearing condition] Bit 8 is reserved. This bit is always read as 0. The write value should always be 0.
Only 1 can be written for clearing the flag.
Rev. 0.5, 03/03, page 277 of 438
11.3.9
Receive Complete Register (RXPR)
RXPR is a status register that indicates the normal reception of messages (data frame or remote frame) in mailboxes (buffers). For reception of a remote frame, when a bit in this register is set to 1, the corresponding remote request register (RFPR) bit is also set to 1 simultaneously.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* * Description When the message in mailbox n (n = 0 to 15) has been received error-free, RXPRn is set to 1. [Setting condition] * Completion of message (data frame or remote frame) reception in corresponding mailbox Writing 1
[Clearing condition]
Only 1 can be written for clearing the flag.
Rev. 0.5, 03/03, page 278 of 438
11.3.10 Remote Request Register (RFPR) RFPR is a status register that indicates normal reception of remote frames in mailboxes (buffers). When a bit in this register is set to 1, the corresponding receive complete register (RXPR) bit is also set to 1 simultaneously.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description When mailbox n (n = 0 to 15) has received the remote frame error-free, RFPRn (n = 0 to 15) is set to 1. [Setting condition] * Completion of remote frame reception in corresponding mailbox Writing 1
[Clearing condition] *
Only 1 can be written for clearing the flag.
Rev. 0.5, 03/03, page 279 of 438
11.3.11 Interrupt Register (IRR) IRR is an interrupt flag register.
Bit 15 Bit Name IRR7 Initial Value 0 R/W R/(W)* Description Overload Frame [Setting condition] * When an overload frame is transmitted in error active/passive state Writing 1
[Clearing condition] * 14 IRR6 0 R/(W)* Bus Off Interrupt Flag Status flag indicating the bus off state caused by the transmit error counter. [Setting condition] * * 13 IRR5 0 R/(W)* When TEC 256 Writing 1 [Clearing condition] Error Passive Interrupt Flag Status flag indicating the error passive state caused by the transmit/receive error counter. [Setting condition] When TEC 128 or REC 128 [Clearing condition] * 12 IRR4 0 R/(W)* Writing 1 Receive Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the receive error counter. [Setting condition] When REC 96 [Clearing condition] * Writing 1
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Bit 11
Bit Name IRR3
Initial Value 0
R/W R/(W)*
Description Transmit Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the transmit error counter. [Setting condition] * * When TEC 96 Writing 1 [Clearing condition]
10
IRR2
0
R
Remote Frame Request Interrupt Flag Status flag indicating that a remote frame has been received in a mailbox (buffer). [Setting condition] * When remote frame reception is completed, when corresponding MBIMR = 0 Clearing of all bits in RFPR (remote request register)
[Clearing condition] * 9 IRR1 0 R
Receive Message Interrupt Flag Status flag indicating that a mailbox (buffer) receive message has been received normally. [Setting condition] * When data frame or remote frame reception is completed, when corresponding MBIMR = 0 Clearing of all bits in RXPR (receive complete register)
[Clearing condition] *
Rev. 0.5, 03/03, page 281 of 438
Bit 8
Bit Name IRR0
Initial Value 1
R/W R/(W)*
Description Reset Interrupt Flag Status flag indicating that the HCAN module has been reset. This bit cannot be masked by the interrupt mask register (IMR). If this bit is not cleared to 0 after entering power-on reset or returning from software standby mode, interrupt processing will start immediately when the interrupt controller enables interrupts. [Setting condition] * When the reset operation has finished after entering power-on reset or software standby mode Writing 1
[Clearing condition] * 7 to 5 All 0 Reserved These bits are always read as 0. Only 0 should be written to these bits. 4 IRR12 0 R/(W)* Bus Operation Interrupt Flag Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. [Setting condition] * Bus operation (dominant bit) detection in HCAN sleep mode Writing 1
[Clearing condition] * 3 2 1 IRR9 0 0 0 R Reserved These bits are always read as 0. Only 0 should be written to these bits. Unread Interrupt Flag Status flag indicating that a receive message has been overwritten before being read. [Setting condition] * When UMSR (unread message status register) is set Clearing of all bits in UMSR (unread message status register)
[Clearing condition] *
Rev. 0.5, 03/03, page 282 of 438
Bit 0
Bit Name IRR8
Initial Value 0
R/W R/(W)*
Description Mailbox Empty Interrupt Flag Status flag indicating that the next transmit message can be stored in the mailbox. [Setting condition] * When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort Writing 1
[Clearing condition] * Note: * Only 1 can be written for clearing the flag.
11.3.12
Mailbox Interrupt Mask Register (MBIMR)
MBIMR controls the enabling or disabling of individual mailbox (buffer) interrupt requests.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Mailbox Interrupt Mask (MBIMRx) When MBIMRn (n = 1 to 15) is cleared to 0, the interrupt request in mailbox n is enabled. When set to 1, the interrupt request is masked. The interrupt source in a transmit mailbox is TXPR clearing caused by transmission end or transmission cancellation. The interrupt source in a receive mailbox is RXPR setting on reception end.
Rev. 0.5, 03/03, page 283 of 438
11.3.13
Interrupt Mask Register (IMR)
IMR enables or disables interrupt requests by the IRR interrupt flags. The reset interrupt flag cannot be masked.
Bit 15 Bit Name IMR7 Initial Value 1 R/W R/W Description Overload Frame/Bus Off Recovery Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR7) is enabled. When set to 1, OVR0 is masked. 14 IMR6 1 R/W Bus Off Interrupt Mask When this bit is cleared to 0, ERS0 (interrupt request by IRR6) is enabled. When set to 1, ERS0 is masked. 13 IMR5 1 R/W Error Passive Interrupt Mask When this bit is cleared to 0, ERS0 (interrupt request by IRR5) is enabled. When set to 1, ERS0 is masked. 12 IMR4 1 R/W Receive Overload Warning Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR4) is enabled. When set to 1, OVR0 is masked. 11 IMR3 1 R/W Transmit Overload Warning Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR3) is enabled. When set to 1, OVR0 is masked. 10 IMR2 1 R/W Remote Frame Request Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR2) is enabled. When set to 1, OVR0is masked. 9 IMR1 1 R/W Receive Message Interrupt Mask When this bit is cleared to 0, RM1 (interrupt request by IRR1) is enabled. When set to 1, RMI is masked. 8 0 R Reserved This bit is always read as 0. Only 0 should be written to this bit. 7 to 5 All 1 R Reserved These bits are always read as 1. Only 1 should be written to these bits.
Rev. 0.5, 03/03, page 284 of 438
Bit 4
Bit Name IMR12
Initial Value 1
R/W R/W
Description Bus Operation Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR12) is enabled. When set to 1, OVR0 is masked.
3 2 1
IMR9
1 1 1
R R R/W
Reserved These bits are always read as 1. Only 1 should be written to these bits. Unread Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR9) is enabled. When set to 1, OVR0 is masked.
0
IMR8
1
R/W
Mailbox Empty Interrupt Mask When this bit is cleared to 0, SLE0 (interrupt request by IRR8) is enabled. When set to 1, SLE0 is masked.
11.3.14 Receive Error Counter (REC) REC is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. 11.3.15 Transmit Error Counter (TEC) TEC is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol.
Rev. 0.5, 03/03, page 285 of 438
11.3.16
Unread Message Status Register (UMSR)
UMSR is a status register that indicates, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. When overwritten by a new message, data in the unread receive message is lost.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description [Setting condition] When a new message is received before RXPR is cleared [Clearing condition] Writing 1
Only 1 can be written for clearing the flag.
Rev. 0.5, 03/03, page 286 of 438
11.3.17
Local Acceptance Filter Masks (LAFML, LAFMH)
LAFML and LAFMH set the identifier bits of the message to be stored in mailbox 0 as Don't Care. For details, refer to section 11.4.4, Message Reception. The relationship between the identifier bits and mask bits are shown in the following. LAFML
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, ID-7 of the receive message identifier is not compared. When this bit is set to 1, ID-6 of the receive message identifier is not compared. When this bit is set to 1, ID-5 of the receive message identifier is not compared. When this bit is set to 1, ID-4 of the receive message identifier is not compared. When this bit is set to 1, ID-3 of the receive message identifier is not compared. When this bit is set to 1, ID-2 of the receive message identifier is not compared. When this bit is set to 1, ID-1 of the receive message identifier is not compared. When this bit is set to 1, ID-0 of the receive message identifier is not compared. When this bit is set to 1, ID-15 of the receive message identifier is not compared. When this bit is set to 1, ID-14 of the receive message identifier is not compared. When this bit is set to 1, ID-13 of the receive message identifier is not compared. When this bit is set to 1, ID-12 of the receive message identifier is not compared. When this bit is set to 1, ID-11 of the receive message identifier is not compared. When this bit is set to 1, ID-10 of the receive message identifier is not compared. When this bit is set to 1, ID-9 of the receive message identifier is not compared. When this bit is set to 1, ID-8 of the receive message identifier is not compared.
Rev. 0.5, 03/03, page 287 of 438
LAFMH
Bit 15 14 13 12 to 10 Bit Name LAFMH7 LAFMH6 LAFMH5 Initial Value 0 0 0 All 0 R/W R/W R/W R/W R Description When this bit is set to 1, ID-20 of the receive message identifier is not compared. When this bit is set to 1, ID-19 of the receive message identifier is not compared. When this bit is set to 1, ID-18 of the receive message identifier is not compared. Reserved These bits are always read as 0. Only 0 should be written to these bits. 9 8 7 6 5 4 3 2 1 0 LAFMH1 LAFMH0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set to 1, ID-17 of the receive message identifier is not compared. When this bit is set to 1, ID-16 of the receive message identifier is not compared. When this bit is set to 1, ID-28 of the receive message identifier is not compared. When this bit is set to 1, ID-27 of the receive message identifier is not compared. When this bit is set to 1, ID-26 of the receive message identifier is not compared. When this bit is set to 1, ID-25 of the receive message identifier is not compared. When this bit is set to 1, ID-24 of the receive message identifier is not compared. When this bit is set to 1, ID-23 of the receive message identifier is not compared. When this bit is set to 1, ID-22 of the receive message identifier is not compared. When this bit is set to 1, ID-21 of the receive message identifier is not compared.
Rev. 0.5, 03/03, page 288 of 438
11.3.18
Message Control (MC0 to MC15)
The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message control registers are in RAM, their initial values after power-on are undefined. Be sure to initialize them by writing 0 or 1. Figure 11.2 shows the register names for each mailbox.
Mail box 0 Mail box 1 Mail box 2 Mail box 3
MC0[1] MC1[1] MC2[1] MC3[1]
MC0[2] MC1[2] MC2[2] MC3[2]
MC0[3] MC1[3] MC2[3] MC3[3]
MC0[4] MC1[4] MC2[4] MC3[4]
MC0[5] MC1[5] MC2[5] MC3[5]
MC0[6] MC1[6] MC2[6] MC3[6]
MC0[7] MC1[7] MC2[7] MC3[7]
MC0[8] MC1[8] MC2[8] MC3[8]
Mail box 15
MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8]
Figure 11.2 Message Control Register Configuration The setting of message control registers are shown in the following. Figures 11.3 and 11.4 show the correspondence between the identifiers and register bit names.
SOF
ID-28
ID-27 identifier
ID-18
RTR
IDE
R0
Figure 11.3 Standard Format
SOF
ID-28 ID-27
ID-18
SRR
IDE
ID-17 ID-16 Extended identifier
ID-0
RTR
R1
Standard identifier
Figure 11.4 Extended Format
Rev. 0.5, 03/03, page 289 of 438
Register Name MCx[1]
Bit 7 to 4 3 to 0
Bit Name DLC3 to DLC0
R/W R/W R/W
Description The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). Data Length Code Set the data length of a data frame or the data length requested in a remote frame within the range of 0 to 8 bits. 0000: 0 byte 0001: 1 byte 0010: 2 bytes 0011: 3 bytes 0100: 4 bytes 0101: 5 bytes 0110: 6 bytes 0111: 7 bytes 1000: 8 bytes : : 1111: 8 bytes
MCx[2] MCx[3] MCx[4] MCx[5]
7 to 0 7 to 0 7 to 0 7 to 5 4
ID-20 to ID-18 RTR
R/W R/W R/W R/W R/W
The initial value of these bits is undefined; they must be initialized (by writing 0 or 1).
Sets ID-20 to ID-18 in the identifier. Remote Transmission Request Used to distinguish between data frames and remote frames. 0: Data frame 1: Remote frame
3
IDE
R/W
Identifier Extension Used to distinguish between the standard format and extended format of data frames and remote frames. 0: Standard format 1: Extended format
2 1 to 0 MCx[6] MCx[7] MCx[8] 7 to 0 7 to 0 7 to 0
ID-17 to ID-16 ID-28 to ID-21 ID-7 to ID-0 ID-15 to ID-8
R/W R/W R/W R/W R/W
The initial value of this bit is undefined. It must be initialized by writing 0 or 1. Sets ID-17 and ID-16 in the identifier. Sets ID-28 to ID-21 in the identifier. Sets ID-7 to ID-0 in the identifier. Sets ID-15 to ID-8 in the identifier.
Note: x: Mailbox number Rev. 0.5, 03/03, page 290 of 438
11.3.19 Message Data (MD0 to MD15) The message data register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message data registers are in RAM, their initial values after poweron are undefined. Be sure to initialize them by writing 0 or 1. Figure 11.5 shows the register names for each mailbox.
Mail box 0 Mail box 1 Mail box 2 Mail box 3
MD0[1] MD1[1] MD2[1] MD3[1]
MD0[2] MD1[2] MD2[2] MD3[2]
MD0[3] MD1[3] MD2[3] MD3[3]
MD0[4] MD1[4] MD2[4] MD3[4]
MD0[5] MD1[5] MD2[5] MD3[5]
MD0[6] MD1[6] MD2[6] MD3[6]
MD0[7] MD1[7] MD2[7] MD3[7]
MD0[8] MD1[8] MD2[8] MD3[8]
Mail box 15
MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8]
Figure 11.5 Message Data Configuration 11.3.20 HCAN Monitor Register (HCANMON)
HCANMON enables/disables an interrupt by the HCAN reception, controls transmit stop by the HTxD pin, and reflects the states of the HCAN pins.
Rev. 0.5, 03/03, page 291 of 438
Bit 7
Bit Name RxDIE
Initial Value 0
R/W R/W
Description HRxD Interrupt Enable Selects whether the IRQ2 interrupt is input from the PF0 pin or HRxD pin. 0: IRQ2 interrupt generated by input of the PF0 pin 1: IRQ2 interrupt generated by input of the HRxD pin
6
TxSTP
0
R/W
HTxD Transmit Stop bit Controls the transmit stop by the HTxD pin. 0: The HTxD pin enables transmission. 1: The HTxD pin is fixed to output 1 and transmission is stopped.
5 to 2
Undefined
Reserved The read value is undefined. These bits cannot be modified.
1
TxD
Undefined
R
Transmission pin The state of the HTxD pin is read. This bit cannot be modified.
0
RxD
Undefined
R
Reception pin The state of the HRxD pin is read. This bit cannot be modified.
Rev. 0.5, 03/03, page 292 of 438
11.4
11.4.1
Operation
Hardware and Software Resets
The HCAN can be reset by a hardware reset or software reset. * Hardware Reset At power-on reset, or in hardware or software standby mode, the HCAN is initialized by automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR. At the same time, all internal registers, except for message control and message data registers, are initialized by a hardware reset. * Software Reset The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In a software reset, the error counters (TEC and REC) are initialized, however other registers are not. If the MCR0 bit is set while the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until message transfer has been completed. The reset status bit (GSR3) in GSR is set on completion of initialization. 11.4.2 Initialization after Hardware Reset
After a hardware reset, the following initialization processing should be carried out: 1. Clearing of IRR0 bit in the interrupt register (IRR) 2. Bit rate setting 3. Mailbox transmit/receive settings 4. Mailbox (RAM) initialization 5. Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which the GSR3 bit in GSR is set to 1 by a reset. Configuration mode is exited by clearing the MCR0 bit in MCR to 0; when the MCR0 bit is cleared to 0, the HCAN automatically clears the GSR3 bit in GSR. There is a delay between clearing the MCR0 bit and clearing the GSR3 bit because the HCAN needs time to be internally reset, there is a delay between clearing of the MCR0 bit and GSR3 bit. After the HCAN exits configuration mode, the power-up sequence begins, and communication with the CAN bus is possible as soon as 11 consecutive recessive bits have been detected. IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared.
Rev. 0.5, 03/03, page 293 of 438
Hardware reset
: Settings by user : Processing by hardware
MCR0 = 1 (automatic)
IRR0 = 1 (automatic) GSR3 = 1 (automatic)
Initialization of HCAN module
Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method initialization
Bit configuration mode Period in which BCR, MBCR, etc., are initialized
MCR0 = 0
GSR3 = 0? Yes IMR setting (interrupt mask setting) MBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting)
No
GSR3 = 0 & 11 recessive bits received? Yes
No
Can bus communication enabled
Figure 11.6 Hardware Reset Flowchart
Rev. 0.5, 03/03, page 294 of 438
MCR0 = 1 : Settings by user Bus idle? Yes GSR3 = 1 (automatic) Initialization of REC and TEC only No : Processing by hardware
BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization OK? Yes MCR0 = 0
Correction No
GSR3 = 0? Yes
No
Correction IMR setting MBIMR setting MC[x] setting LAFM setting OK?
No
Yes
GSR3 = 0 & 11 recessive bits received? Yes CAN bus communication enabled
No
Figure 11.7 Software Reset Flowchart
Rev. 0.5, 03/03, page 295 of 438
Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit configuration register (BCR). Settings should be made such that all CAN controllers connected to the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the settable time quantum (tq).
1-bit time (8-25 time quanta)
SYNC_SEG
PRSEG
PHSEG1
PHSEG2 Time segment 2 (TSEG2)
Time segment 1 (TSEG1) 1 time quantum 2-16 time quanta
Figure 11.8 Detailed Description of One Bit SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer segment for correcting phase drift (negative). This segment is shortened when synchronization (resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, sample point, and SJW) are shown in table 11.2. Table 11.2 Limits for Settable Value
Name Time segment 1 Time segment 2 Baud rate prescaler Bit sample point Re-synchronization jump width Abbreviation TSEG1 TSEG2 BRP BSP SJW*
1
Min. Value B'0011* B'001*
3 2
Max. Value B'1111 B'111 B'111111 B'1 B'11
B'000000 B'0 B'00
Notes: 1. SJW is stipulated in the CAN specifications: 3 SJW 0 2. The minimum value of TSEG2 is stipulated in the CAN specifications: TSEG2 SJW 3. The minimum value of TSEG1 is stipulated in the CAN specifications: TSEG1 > TSEG2
Rev. 0.5, 03/03, page 296 of 438
Time Quanta (TQ) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (BRP) as follows. fCLK is the system clock frequency. TQ = 2 x (BPR setting + 1)/fCLK The following formula is used to calculate the 1-bit time and bit rate. 1-bit time = TQ x (3 + TSEG1 + TSEG2) Bit rate = 1/Bit time = fCLK/{2 x (BPR setting + 1) x (3 + TSEG1 + TSEG2)} Note: fCLK = (system clock) A BCR value is used for BRP, TSEG1, and TSEG2.
Example: With a system clock of 24 MHz, a BRP setting of B'000000, a TSEG1 setting of B'0101, and a TSEG2 setting of B100: Bit rate = 24/{2 x (0 + 1) x (3 + 5 + 4)} = 1 Mbps Table 11.3 Setting Range for TSEG1 and TSEG2 in BCR
TSEG2 (BCR[14:12]) 001 TSEG1 (BCR[11:8]) 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Note: * No Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* 010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 011 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 100 No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 101 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 110 No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 111 No No No No No Yes Yes Yes Yes Yes Yes Yes Yes
The time quantum value for TSEG1 and TSEG2 is the TSEG value + 1. Only a value other than BRP[13:8] = B'000000 can be set.
Mailbox Transmit/Receive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. The Initial status of mailboxes 1 to 15 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset.
Rev. 0.5, 03/03, page 297 of 438
Mailbox Transmit/Receive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. The Initial status of mailboxes 1 to 15 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset. Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding mailbox for reception use. When setting mailboxes for reception, in order to improve message reception efficiency, high-priority messages should be set in low-to-high mailbox order. Mailbox (Message Control/Data) Initial Settings: Message control/data are held in RAM, and so their initial values are undefined after power is supplied. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: The following two kinds of message transmission methods are available. * Transmission order determined by message identifier priority * Transmission order determined by mailbox number priority Either of the message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): When messages are set to be transmitted according to the message identifier priority, if several messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority in the message identifier is stored in the transmit buffer. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. When the TXPR bit is set, the highest-priority message is found and stored in the transmit buffer. When messages are set to be transmitted according to the mailbox number proiority, if several messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired.
Rev. 0.5, 03/03, page 298 of 438
11.4.3
Message Transmission
Messages are transmitted using mailboxes 1 to 15. The transmission procedure after initial settings is described below, and a transmission flowchart is shown in figure 11.9.
Initialization (after hardware reset only) Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method setting Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting
: Settings by user : Processing by hardware
Message transmission wait TXPR setting
Bus idle?
No
Yes Message transmission GSR2 = 0 (during transmission only)
Transmission completed?
No
Yes TXACK = 1 IRR8 = 1
IMR8 = 1?
Yes
No Interrupt to CPU Clear TXACK Clear IRR8
End of transmission
Figure 11.9 Transmission Flowchart
Rev. 0.5, 03/03, page 299 of 438
CPU interrupt source settings: The CPU interrupt source is set by the interrupt mask register (IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and transmission abort acknowledge interrupts can be generated for individual mailboxes in the mailbox interrupt mask register (MBIMR). Arbitration field setting: The arbitration field is set by message control registers MCx[5]- MCx[8] in a transmit mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and the RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28 to ID-0) and the RTR bit are set, and the IDE bit is set to 1. Control field setting: In the control field, the byte length of the data to be transmitted is set within the range of zero to eight bytes. The register to be set is the message control register MCx[1] in a transmit mailbox. Data field setting: In the data field, the data to be transmitted is set within the range zero to eight. The registers to be set are the message data registers MDx[1]-MDx[8]. The byte length of the data to be transmitted is determined by the data length code in the control field. Even if data exceeding the value set in the control field is set in the data field, up to the byte length set in the control field will actually be transmitted. Message transmission: If the corresponding mailbox transmit wait bit (TXPR1-TXPR15) in the transmit wait register (TXPR) is set to 1 after message control and message data registers have been set, the message enters transmit wait state. If the message is transmitted error-free, the corresponding acknowledge bit (TXACK1-TXACK15) in the transmit acknowledge register (TXACK) is set to 1, and the corresponding transmit wait bit (TXPR1-TXPR15) in the transmit wait register (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU. If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: * CAN bus arbitration failure (failure to acquire the bus) * Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error) Message transmission cancellation: Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1-TXCR15) to 1 in the transmit cancel register (TXCR). Clearing the transmit wait register (TXPR) does not cancel transmission. When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested, and if the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1-MBIMR15) corresponding
Rev. 0.5, 03/03, page 300 of 438
to the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR), interrupts may be sent to the CPU. However, a transmit wait message cannot be canceled at the following times: * During internal arbitration or CAN bus arbitration * During data frame or remote frame transmission Figure 11.10 shows a flowchart for transmit message cancellation.
Message transmit wait TXPR setting
: Settings by user : Processing by hardware
Set TXCR bit corresponding to message to be canceled
Cancellation possible?
No
Yes Message not sent Clear TXCR, TXPR ABACK = 1 IRR8 = 1 Completion of message transmission TXACK = 1 Clear TXCR, TXPR IRR8 = 1
IMR8 = 1?
Yes
No Interrupt to CPU
Clear TXACK Clear ABACK Clear IRR8
End of transmission/transmission cancellation
Figure 11.10 Transmit Message Cancellation Flowchart
Rev. 0.5, 03/03, page 301 of 438
11.4.4
Message Reception
The reception procedure after initial settings is described below. A reception flowchart is shown in figure 11.11.
Initialization Clear IRR0 BCR setting MBCR setting Mailbox (RAM) initialization Interrupt settings Receive data setting Arbitration field setting Local acceptance filter settings
: Settings by user : Processing by hardware
Message reception (Match of identifier in mailbox?) Yes
No
Same RXPR = 1? No
Yes Unread message
Data frame? Yes RXPR IRR1 = 1
No
RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1
Yes IMR1 = 1? No Interrupt to CPU Message control read Message data read
IMR2 = 1? No Interrupt to CPU Message control read Message data read
Yes
Clear IRR1
Clear IRR2, IRR1 Transmission of data frame corresponding to remote frame
End of reception
Figure 11.11 Reception Flowchart
Rev. 0.5, 03/03, page 302 of 438
CPU interrupt source settings: CPU interrupt source settings are made in the interrupt mask register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also specified. Data frame and remote frame receive wait interrupt requests can be generated for individual mailboxes in the MBIMR. Arbitration field setting: To receive a message, the message identifier must be set in advance in the message control registers (MCx[1]-MCx[8]) for the receiving mailbox. When a message is received, all the bits in the receive message identifier are compared with those in each message control register identifier, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox 0 has a local acceptance filter mask (LAFM) that allows Don't Care settings to be made. The LAFM setting can be made only for mailbox 0. By making the Don't Care setting for all the bits in the receive message identifier, messages of multiple identifiers can be received. Examples: * When the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of message identifier can be received by mailbox 1: Identifier 1: 010_1010_1010 * When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is 000_0000_0011 (0: Care, 1: Don't Care), a total of four kinds of message identifiers can be received by mailbox 0: Identifier 1: Identifier 2: Identifier 3: Identifier 4: 010_1010_1000 010_1010_1001 010_1010_1010 010_1010_1011
Message reception: When a message is received, a CRC check is performed automatically. If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether the message can be received or not. * Data frame reception If the received message is confirmed to be error-free by the CRC check, the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive message, are compared. If a complete match is found, the message is stored in the mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR0-RXPR15) is set in the receive complete register (RXPR). However, when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received by another mailbox. Note that the same message cannot be stored in more than one of mailboxes 1 to 15. On receiving a message, a CPU interrupt request may be generated
Rev. 0.5, 03/03, page 303 of 438
depending on the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR) settings. * Remote frame reception Two kinds of messages--data frames and remote frames--can be stored in mailboxes. A remote frame differs from a data frame in that the remote transmission request bit (RTR) in the message control register and the data field is 0 bytes long. The data length to be returned in a data frame must be stored in the data length code (DLC) in the control field. When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote request wait register (RFPR). If the corresponding bit (MBIMR0-MBIMR15) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Unread message overwrite: If the receive message identifier matches the mailbox identifier, the receive message is stored in the mailbox regardless of whether the mailbox contains an unread message or not. If a message overwrite occurs, the corresponding bit (UMSR0-UMSR15) is set in the unread message register (UMSR). In overwriting an unread message, when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Figure 11.12 shows a flowchart for unread message overwriting.
: Settings by user : Processing by hardware UMSR = 1 IRR9 = 1
Unread message overwrite
IMR9 = 1?
Yes
No Interrupt to CPU
Clear IRR9 Message control/message data read
End
Figure 11.12 Unread Message Overwrite Flowchart
Rev. 0.5, 03/03, page 304 of 438
11.4.5
HCAN Sleep Mode
The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state in order to reduce current consumption. Figure 11.13 shows a flowchart of the HCAN sleep mode.
MCR5 = 1 : Settings by user : Processing by hardware
Bus idle?
No
Initialize TEC and REC
Bus operation? Yes IRR12 = 1
No
IMR12 = 1?
No CPU interrupt
Yes
Sleep mode clearing method MCR7 = 0? Yes (manual) MCR5 = 0
No (automatic)
Clear sleep mode?
No
Yes MCR5 = 0
11 recessive bits? Yes CAN bus communication possible
No
Figure 11.13 HCAN Sleep Mode Flowchart
Rev. 0.5, 03/03, page 305 of 438
HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected: * Clearing by software * Clearing by CAN bus operation Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus communication is re-enabled. Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU. Clearing by CAN bus operation: The cancellation method is selected by the MCR7 bit setting in MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not stored in a mailbox; messages will be received normally from the second message onward. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 11.4.6 HCAN Halt Mode
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 11.14 shows a flowchart of the HCAN halt mode.
MCR1 = 1
Bus idle?
No
Yes MBCR setting
MCR1 = 0
: Settings by user CAN bus communication possible : Processing by hardware
Figure 11.14 HCAN Halt Mode Flowchart
Rev. 0.5, 03/03, page 306 of 438
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0.
11.5
Interrupt Sources
Table 11.4 lists the HCAN interrupt sources. With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is implemented using the mailbox interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER). For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller. Table 11.4 HCAN Interrupt Sources
Name ERS0/OVR0 Description Error passive interrupt (TEC 128 or REC 128) Bus off interrupt (TEC 256) Reset process interrupt by power-on reset Remote frame reception Error warning interrupt (TEC 96) Error warning interrupt (REC 96) Overload frame transmission Unread message overwrite Detection of CAN bus operation in HCAN sleep mode RM0 RM1 SLE0 IRQ2 Mailbox 0 message reception Mailbox 1-15 message reception Message transmission/cancellation Generation of IRQ2 interrupt from HRxD input pin by setting RxDIE bit in HCANMON to 1 Interrupt Flag IRR5 IRR6 IRR0 IRR2 IRR3 IRR4 IRR7 IRR9 IRR12 IRR1 IRR1 IRR8 IRQ2F
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11.6
CAN Bus Interface
A bus transceiver IC is necessary to connect this chip to a CAN bus. A Philips PCA82C250 transceiver IC is recommended. Any other product must be compatible with the PCA82C250. Figure 11.15 shows a sample connection diagram.
124 Vcc PCA82C250 RS HRxD HTxD NC 124 Note: NC: No Connection Vcc CAN bus
This LSI
RxD CANH TxD CANL Vref GND
Figure 11.15 High-Speed Interface Using PCA82C250
11.7
11.7.1
Usage Notes
Module Stop Mode Setting
HCAN operation can be disabled or enabled using the module stop control register. The initial setting is for HCAN operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 16, Power-Down Modes. 11.7.2 Reset
The HCAN is reset by a power-on reset, in hardware standby mode, and in software standby mode. All the registers are initialized in a reset, however mailboxes (message control (MCx[x])/message data (MDx[x])) are not. After power-on, mailboxes (message control (MCx[x])/message data (MDx[x])) are initialized, and their values are undefined. Therefore, mailbox initialization must always be carried out after a power-on reset, a transition to hardware standby mode, or software standby mode. The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As this bit cannot be masked in the interrupt mask register (IMR), if HCAN interrupt enabling is set in the interrupt controller without clearing the flag, an HCAN interrupt will be initiated immediately. IRR0 should therefore be cleared during initialization.
Rev. 0.5, 03/03, page 308 of 438
11.7.3
HCAN Sleep Mode
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set in sleep mode. 11.7.4 Interrupts
When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8, 2, 1) is not set by reception completion, transmission completion, or transmission cancellation for the set mailboxes. 11.7.5 Error Counters
In the case of error active and error passive, REC and TEC normally count up and down. In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96 during the count, IRR4 and GSR1 are set. 11.7.6 Register Access
Byte or word access can be used on all HCAN registers. Longword access cannot be used. 11.7.7 HCAN Medium-Speed Mode
In medium-speed mode, neither read nor write is possible for the HCAN registers. 11.7.8 Register Hold in Standby Modes
All HCAN registers are initialized in hardware standby mode and software standby mode. 11.7.9 Use on Bit Manipulation Instructions
Since the HCAN status flag is cleared by writing 1, do not use the bit manipulation instructions to clear the flag. To clear the flag, use the MOV instructions and write 1 only to the bit to be cleared.
Rev. 0.5, 03/03, page 309 of 438
11.7.10 HCAN TXCR Operation 1. When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a transmit wait mailbox, the corresponding bit to TXCR and the transmit wait register (TXPR) may not be cleared even if transmission is canceled. This occurs when the following conditions are all satisfied.
* The HRxD pin is stacked to 1 because of a CAN bus error, etc. * There is at least one mailbox waiting for transmission or being transmitted. * The message transmission in a mailbox being transmitted is canceled by TXCR. If this occurs, transmission is canceled. However, since TXPR and TXCR states are indicated wrongly that a message is being cancelled, transmission cannot be restarted even if the stack state of the HRxD pin is canceled and the CAN bus recovers the normal state. If there are at least two transmission messages, a message which is not being transmitted is canceled and a message being transmitted retains its state. To avoid this, one of the following countermeasures must be executed. * Transmission must not be canceled by TXCR. When transmission is normally completed after the CAN bus has recovered, TXPR is cleared and the HCAN recovers the normal state. * To cancel transmission, the corresponding bit to TXCR must be written to 1 continuously until the bit becomes 0. TXPR and TXCR are cleared and the HCAN recovers the normal state. 2. When the bus-off state is entered while TXPR is set and the transmit wait state is entered, the internal state machine does not operate even if TXCR is set during the bus-off state. Therefore transmission cannot be canceled. The message can be canceled when one message is transmitted or a transmission error occurs after the bus-off state is recovered. To clear a message after the bus-off state is recovered, the following countermeasure must be executed. * A transmit wait message must be cleared by resetting the HCAN during the bus-off period. To reset the HCAN, the module stop bit (MSTPC3 in MSTPCRC) must be set or cleared. In this case, the HCAN is entirely reset. Therefore the initial settings must be made again.
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Section 12 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to 16 analog input channels to be selected. The block diagram of the A/D converter is shown in figure 12.1.
12.1
Features
* 10-bit resolution * 16 input channels * Conversion time: 11.08 s per channel (at 24 MHz operation) * Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three methods conversion start Software 16-bit timer pulse unit (TPU) conversion start trigger External trigger signal * Interrupt request An A/D conversion end interrupt request (ADI) can be generated * Module stop mode can be set
ADCMS00B_000020020200
Rev. 0.5, 03/03, page 311 of 438
Module data bus
Bus interface
Internal data bus
AVCC 10-bit D/A AVSS
Successive approximations register
A D D R A
A D D R B
A D D R C
A D D R D
A D C S R
A D C R
AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
Multiplexer
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
+
/2 /4
Comparator Sample-andhold circuit
Control circuit
/8 /16
ADI interrupt Conversion start trigger from TPU
Legend ADCR ADCSR ADDRA ADDRB ADDRC ADDRD
: : : : : :
A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
Figure 12.1 Block Diagram of A/D Converter
Rev. 0.5, 03/03, page 312 of 438
12.2
Input/Output Pins
Table 12.1 summarizes the input pins used by the A/D converter. The 16 analog input pins are divided into four channel sets and four groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1, analog input pins 8 to 11 (AN8 to AN11) comprising group 2, and analog input pins 12 to 15 (AN12 to AN15) comprising group 3. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. Table 12.1 Pin Configuration
Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 A/D external trigger input pin Symbol AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input pin for starting A/D conversion Group 3 analog input pins Group 2 analog input pins Group 1 analog input pins Function Analog block power supply and reference voltage Analog block ground and reference voltage Group 0 analog input pins
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12.3
Register Descriptions
The A/D converter has the following registers. The MSTPA1 bit in the module stop control register A (MSTPCRA) specifies the modes of this module as module stop mode. For details on MSTPCRA, refer to section 16.1.3, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC). * A/D data register A (ADDRA) * A/D data register B (ADDRB) * A/D data register C (ADDRC) * A/D data register D (ADDRD) * A/D control/status register (ADCSR) * A/D control register (ADCR) 12.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 12.2. The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read the upper byte before the lower byte, or read in word unit. When only the lower byte is read, the contents are not guaranteed. Table 12.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel CH3 = 0 Group 0 (CH2 = 0) AN0 AN1 AN2 AN3 Group 1 (CH2 = 1) AN4 AN5 AN6 AN7 Group 2 (CH2 = 0) AN8 AN9 AN10 AN11 CH3 = 1 Group 3 (CH2 = 1) AN12 AN13 AN14 AN15 A/D Data Register to be Stored Results of A/D Conversion ADDRA ADDRB ADDRC ADDRD
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12.3.2
A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit 7 Bit Name ADF Initial Value 0 R/W R/(W) Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends When A/D conversion ends on all specified channels When 0 is written after reading ADF = 1
[Clearing condition] * 6 ADIE 0 R/W A/D Interrupt Enable A/D conversion end interrupt (ADI) request enabled when 1 is set 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters the wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bits is cleared to 0 automatically when conversion on the specified channel is complete. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to software standby mode, hardware standby mode or module stop mode. 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode
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Bit 3 2 1 0
Bit Name CH3 CH2 CH1 CH0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description Channel Select 0 to 3 Select analog input channels. When SCAN = 0 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1000: AN8 1001: AN9 1010: AN10 1011: AN11 1100: AN12 1101: AN13 1110: AN14 1111: AN15 When SCAN = 1 0000: AN0 0001: AN0, AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4, AN5 0110: AN4 to AN6 0111: AN4 to AN7 1000: AN8 1001: AN8, AN9 1010: AN8 to AN10 1011: AN8 to AN11 1100: AN12 1101: AN12, AN13 1110: AN12 to AN14 1111: AN12 to AN15
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12.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 0 and 1 Enables the start of A/D conversion by a trigger signal. Only set bits TRGS0 and TRGS1 while conversion is stopped (ADST = 0). 00: A/D conversion start by software is enabled 01: A/D conversion start by TPU conversion start trigger is enabled 10: Setting prohibited 11: A/D conversion start by external trigger pin (ADTRG) is enabled 5 4 3 2 CKS1 CKS0 1 1 0 0 R/W R/W Reserved These bits are always read as 1. Clock Select 0 and 1 These bits specify the A/D conversion time. The conversion time should be changed only when ADST = 0. Specify a setting that gives a value within the range shown in table 18.7 in section 18, Electrical Characteristics. 00: Conversion time = 530 states (max.) 01: Conversion time = 266 states (max.) 10: Conversion time = 134 states (max.) 11: Conversion time = 68 states (max.) 1 0 1 1 Reserved These bits are always read as 1.
Rev. 0.5, 03/03, page 317 of 438
12.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 12.4.1 Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit is set to 1, according to software or external trigger input. 2. When A/D conversion is completed, the result is transferred to the corresponding A/D data register to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D converion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the wait state. 12.4.2 Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels maximum). The operations are as follows. 1. When the ADST bit is set to 1 by software, TPU or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH3 and CH2 = 00, AN4 when CH3 and CH2 = 01, AN8 when CH3 and CH2 = 10, or AN12 when CH3 and CH2 = 11). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. Steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the wait state.
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12.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 12.2 shows the A/D conversion timing. Table 12.3 shows the A/D conversion time. As indicated in figure 12.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 12.3. In scan mode, the values given in table 12.3 apply to the first conversion time. The values given in table 12.4 apply to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0 in ADCR to give an A/D conversion time within the range shown in table 18.7 in section 18, Electrical Characteristics.
(1) Address (2)
Write signal Input sampling timing
ADF tD tSPL tCONV Legend (1) : ADCSR write cycle (2) : ADCSR address : A/D conversion start delay tD tSPL : Input sampling time tCONV : A/D conversion time
Figure 12.2 A/D Conversion Timing
Rev. 0.5, 03/03, page 319 of 438
Table 12.3 A/D Conversion Time (Single Mode)
CKS1 = 0 CKS0 = 0 Item Symbol Min. Typ. Max. 18 -- -- 33 CKS0 = 1 Min. Typ. Max. 10 -- -- 63 17 -- 266 CKS1 = 1 CKS0 = 0 Min. Typ. Max. 6 -- -- 31 9 -- 134 CKS0 = 1 Min. Typ. Max. 4 -- 67 -- 15 -- 5 -- 68
A/D conversion tD start delay Input sampling tSPL time A/D conversion tCONV time
127 -- 530
515 --
259 --
131 --
Note: All values represent the number of states.
Table 12.4 A/D Conversion Time (Scan Mode)
CKS1 0 CKS0 0 1 1 0 1 Conversion Time (State) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed)
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12.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 12.3 shows the timing.
Internal trigger signal
ADST A/D conversion
Figure 12.3 External Trigger Input Timing
12.5
Interrupt Sources
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the bit ADF in ADCSR is set to 1 after A/D conversion is completed. Table 12.5 A/D Converter Interrupt Source
Name ADI Interrupt Source A/D conversion completed Interrupt Source Flag ADF
Rev. 0.5, 03/03, page 321 of 438
12.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 12.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 12.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and fullscale voltage. Does not include offset error, full-scale error, or quantization error (see figure 12.5). * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
Rev. 0.5, 03/03, page 322 of 438
Digital output
111 110 101 100 011 010 001 000
Ideal A/D conversion characteristic
Quantization error
1 2 1024 1024
1022 1023 FS 1024 1024 Analog input voltage
Figure 12.4 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage
Offset error
Figure 12.5 A/D Conversion Accuracy Definitions
Rev. 0.5, 03/03, page 323 of 438
12.7
12.7.1
Usage Notes
Module Stop Mode Setting
Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 16, Power-Down Modes. 12.7.2 Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 12.6). When converting a high-speed analog signal, a low-impedance buffer should be inserted. 12.7.3 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e, acting as antennas).
This LSI Sensor output impedance to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF
A/D converter equivalent circuit 10 k 20 pF
Figure 12.6 Example of Analog Input Circuit
Rev. 0.5, 03/03, page 324 of 438
12.7.4
Range of Analog Power Supply and Other Pin Settings
If the conditions below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ANn AVcc. * Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. 12.7.5 Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN15), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. 12.7.6 Notes on Noise Countermeasures
A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN15), between AVcc and AVss, as shown in figure 12.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN15 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants.
Rev. 0.5, 03/03, page 325 of 438
AVCC Rin*2 *1 0.1 F 100 AN0 to AN15 AVSS
Notes: Values are reference values. 1. 10 F 0.01 F
2. Rin: Input impedance
Figure 12.7 Example of Analog Input Protection Circuit Table 12.6 Analog Pin Specifications
Item Analog input capacitance Permissible signal source impedance Min. Max. 20 5 Unit pF k
10 k AN0 to AN15 To A/D converter 20 pF
Note: Values are reference values.
Figure 12.8 Analog Input Pin Equivalent Circuit
Rev. 0.5, 03/03, page 326 of 438
Section 13 RAM
This LSI has 4 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR).
Rev. 0.5, 03/03, page 327 of 438
Rev. 0.5, 03/03, page 328 of 438
Section 14 ROM
The features of the flash memory are summarized below. The block diagram of the flash memory is shown in figure 14.1.
14.1
Features
* Size: 64 kbytes * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 28 kbytes x 1 block, 16 kbytes x 1 block, 8 kbytes x 2 blocks, and 1 kbyte x 4 blocks. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * Three programming modes Boot mode User mode Programmer mode On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing.
ROM3120A_000020020200
Rev. 0.5, 03/03, page 329 of 438
Internal address bus
Internal data bus (16 bits)
Module bus
FLMCR1 FLMCR2 EBR1 RAMER FLPWCR Bus interface/controller Operating mode FWE pin Mode pin
Flash memory (64 kbytes)
Legend FLMCR1: FLMCR2: EBR1: RAMER: FLPWCR:
Flash memory control register 1 Flash memory control register 2 Erase block register 1 RAM emulation register Flash memory power control register
Figure 14.1
Block Diagram of Flash Memory
14.2
Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 14.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 14.1. Figure 14.3 shows the operation flow for boot mode and figure 14.4 shows that for user program mode.
Rev. 0.5, 03/03, page 330 of 438
MD1 = 1, MD2 = 1, FWE = 0 *1 User mode (on-chip ROM enabled) =0
Reset state
=0 MD1 = 1, MD2 = 1, FWE = 1 =0 MD2 = 0 MD1 = 1, FWE = 1 =0 Programmer mode *2
FWE = 1
FWE = 0
User program mode
*1
Boot mode On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. This LSI transits to programmer mode by using the dedicated PROM programmer.
Figure 14.2 Flash Memory State Transitions Table 14.1 Differences between Boot Mode and User Program Mode
Boot Mode Total erase Block erase Programming control program* Yes No (2) User Program Mode Yes Yes (1) (2) (3)
(1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm.
Rev. 0.5, 03/03, page 331 of 438
1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host.
2. Programming control program transfer When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area.
Host
Host Programming control program New application program
; ;;; ;;
New application program
This LSI
This LSI
Boot program
SCI
Boot program
SCI
Flash memory
RAM
Flash memory
RAM
Boot program area
Programming control program
Application program (old version)
Application program (old version)
3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks.
Host
4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory.
Host
New application program
This LSI
This LSI
Boot program
SCI
Boot program
SCI
Flash memory
RAM
Flash memory
RAM
Boot program area
Programming control program
Boot program area
Programming control program
Flash memory preprogramming erase
New application program
Program execution state
Figure 14.3 Boot Mode
Rev. 0.5, 03/03, page 332 of 438
;; ;;
Host Host Programming/ erase control program New application program New application program
1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory.
2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM.
This LSI
This LSI
Boot program
SCI
Boot program
SCI
Flash memory
RAM
Flash memory
RAM
FWE assessment program
FWE assessment program
Transfer program
Transfer program
Programming/ erase control program
Application program (old version)
Application program (old version)
3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units.
Host
4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks.
Host
New application program
This LSI
This LSI
Boot program
SCI
Boot program
SCI
Flash memory
RAM
Flash memory
RAM
FWE assessment program
Transfer program
FWE assessment program Transfer program
Programming/ erase control program
Programming/ erase control program
Flash memory erase
New application program
Program execution state
Figure 14.4 User Program Mode
Rev. 0.5, 03/03, page 333 of 438
14.3
Block Configuration
Figure 14.5 shows the block configuration of 64-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 28 kbytes (1 block), 16 kbytes (1 block), 8 kbytes (2 blocks), and 1 kbyte (4 blocks). Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
EB0 Erase unit 1 kbyte EB1 Erase unit 1 kbyte EB2 Erase unit 1 kbyte EB3 Erase unit 1 kbyte EB4 Erase unit 28 kbytes EB5 Erase unit 16 kbytes EB6 Erase unit 8 kbytes EB7 Erase unit 8 kbytes
H'000000 H'000380 H'000400
H'000001 H'000381 H'000401
H'000002 H'000382 H'000402
Programming unit: 128 bytes
H'00007F H'0003FF
Programming unit: 128 bytes
H'00047F H'0007FF
H'000780 H'000800 H'000B80 H'000C00
H'000781 H'000801 H'000B81 H'000C01
H'000782 H'000802 H'000B82 H'000C02 Programming unit: 128 bytes Programming unit: 128 bytes
H'00087F
H'000BFF H'000C7F H'000FFF Programming unit: 128 bytes H'00107F H'007FFF Programming unit: 128 bytes H'00807F H'00BFFF Programming unit: 128 bytes H'00C07F H'00DFFF Programming unit: 128 bytes H'00E07F
H'000F80 H'001000 H'007F80 H'008000 H'00BF80 H'00C000
H'000F81 H'001001 H'007F81 H'008001 H'00BF81 H'00C001
H'000F82 H'001002 H'007F82 H'008002 H'00BF82 H'00C002
H'00DF80 H'00E000 H'00FF80
H'00DF81 H'00E001 H'00FF81
H'00DF82 H'00E002 H'00FF82
H'00FFFF
Figure 14.5 Flash Memory Block Configuration
Rev. 0.5, 03/03, page 334 of 438
14.4
Input/Output Pins
The flash memory is controlled by means of the pins shown in table 14.2. Table 14.2 Pin Configuration
Pin Name RES FWE MD2 MD1 MD0 TxD2 RxD2 I/O Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Serial transmit data output Serial receive data input
14.5
Register Descriptions
The flash memory has the following registers. * Flash memory control register 1 (FLMCR1) * Flash memory control register 2 (FLMCR2) * Erase block register 1 (EBR1) * RAM emulation register (RAMER) * Flash memory power control register (FLPWCR)
Rev. 0.5, 03/03, page 335 of 438
14.5.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 14.8, Flash Memory Programming/Erasing.
Bit 7 Bit Name FWE Initial Value R/W R Description Reflects the input level at the FWE pin. It is cleared to 0 when a low level is input to the FWE pin, and set to 1 when a high level is input. Software Write Enable Bit When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 bits cannot be set. 5 ESU1 0 R/W Erase Setup Bit When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. 4 PSU1 0 R/W Program Setup Bit When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P1 bit in FLMCR1. 3 EV1 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, eraseverify mode is cancelled. 2 PV1 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, program-verify mode is cancelled. 1 E1 0 R/W Erase When this bit is set to 1, and while the SWE1 and ESU1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P1 0 R/W Program When this bit is set to 1, and while the SWE1 and PSU1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. Rev. 0.5, 03/03, page 336 of 438
6
SWE
0
R/W
14.5.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Bit 7 Bit Name FLER Initial Value 0 R/W R Description Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See section 14.9.3, Error Protection, for details. 6 to 0 All 0 Reserved These bits are always read as 0.
14.5.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0.
Bit 7 6 5 4 3 2 1 0 Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 8 kbytes of EB7 (H'00E000 to H'00FFFF) will be erased. When this bit is set to 1, 8 kbytes of EB6 (H'00C000 to H'00DFFF) will be erased. When this bit is set to 1, 16 kbytes of EB5 (H'008000 to H'00BFFF) will be erased. When this bit is set to 1, 28 kbytes of EB4 (H'001000 to H'007FFF) will be erased. When this bit is set to 1, 1 kbyte of EB3 (H'000C00 to H'000FFF) will be erased. When this bit is set to 1, 1 kbyte of EB2 (H'000800 to H'000BFF) will be erased. When this bit is set to 1, 1 kbyte of EB1 (H'000400 to H'0007FF) will be erased. When this bit is set to 1, 1 kbyte of EB0 (H'000000 to H'0003FF) will be erased.
Rev. 0.5, 03/03, page 337 of 438
14.5.4
RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed.
Bit 7, 6 5, 4 3 Bit Name RAMS Initial Value All 0 All 0 0 R/W R/W R/W Description Reserved These bits are always read as 0. Reserved Only 0 should be written to these bits. RAM Select Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory block are program/erase-protected. 2 1 0 RAM2 RAM1 RAM0 0 0 0 R/W R/W R/W Flash Memory Area Selection When the RAMS bit is set to 1, one of the following flash memory areas are selected to overlap the RAM area of H'FFE000 to H'FFE3FF. The areas correspond with 1-kbyte erase blocks. 00X: H'000000 to H'0003FF (EB0) 01X: H'000400 to H'0007FF (EB1) 10X: H'000800 to H'000BFF (EB2) 11X: H'000C00 to H'000FFF (EB3) Note: X: Don't care
Rev. 0.5, 03/03, page 338 of 438
14.5.5
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when this LSI switches to subactive mode.
Bit 7 6 to 0 Bit Name PDWND -- Initial Value 0 All 0 R/W R/W R Description When this bit is set to 1, the transition to flash memory power-down mode is disabled. Reserved These bits are always read as 0.
14.6
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the MD pin settings and FWE pin setting, as shown in table 14.3. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI_2. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 14.3 Setting On-Board Programming Modes
MD2 1 0 MD1 1 1 MD0 1 1 FWE 1 1 LSI State after Reset End User Mode Boot Mode
Rev. 0.5, 03/03, page 339 of 438
14.6.1
Boot Mode
Table 14.4 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 14.8, Flash Memory Programming/Erasing. 2. SCI_2 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI_2 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 14.5. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFE000 to H'FFE7FF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI_2 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD pin is high. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the mode (MD) pins. Boot mode is also cleared when a WDT overflow occurs. 8. 9. Do not change the MD pin input levels in boot mode. All interrupts are disabled during programming or erasing of the flash memory.
Rev. 0.5, 03/03, page 340 of 438
Table 14.4 Boot Mode Operation
Host Operation Item Boot mode start Processing Contents Communications Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate. H'00, H'00 ...... H'00
Transmits data H'55 when data H'00 is received error-free.
H'00 H'55 H'AA
* Measures low-level period of receive data H'00. * Calculates bit rate and sets it in BRR of SCI_2. * Transmits data H'00 to host as adjustment end indication. Transmits data H'AA to host when data H'55 is received.
Receives data H'AA. Transfer of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) Transmits 1-byte of programming control program (repeated for N times) Flash memory erase Boot program erase error Receives data H'AA. H'FF High-order byte and low-order byte Echobacks the 2-byte data received. Echoback H'XX Echoback Echobacks received data to host and also transfers it to RAM (repeated for N times)
H'AA
Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Branches to programming control program transferred to on-chip RAM and starts execution.
Table 14.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible
Host Bit Rate 19,200 bps 9,600 bps 4,800 bps System Clock Frequency Range of LSI 24 MHz 8 to 24 MHz 4 to 24 MHz
Rev. 0.5, 03/03, page 341 of 438
14.6.2
Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 14.6 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 14.8, Flash Memory Programming/Erasing.
Reset-start
No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program
Branch to user program/erase control program in RAM
FWE=high*
Execute user program/erase control program (flash memory rewrite)
Clear FWE
Branch to flash memory application program Note: * Do not constantly apply a high level to the FWE pin. Only apply a high level to the FWE pin when programming or erasing the flash memory. To prevent excessive programming or excessive erasing, while a high level is being applied to the FWE pin, activate the watchdog timer in case of handling CPU runaways.
Figure 14.6 Programming/Erasing Flowchart Example in User Program Mode
Rev. 0.5, 03/03, page 342 of 438
14.7
Flash Memory Emulation in RAM
A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. Emulation can be performed in user mode or user program mode. Figure 14.7 shows an example of emulation of real-time flash memory programming. 1. Set RAMER to overlap part of RAM onto the area for which real-time programming is required. 2. Emulation is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0).
Start of emulation program
Set RAMER
Write tuning data to overlap RAM
Execute application program No
Tuning OK? Yes Clear RAMER
Write to flash memory emulation block
End of emulation program
Figure 14.7 Flowchart for Flash Memory Emulation in RAM
Rev. 0.5, 03/03, page 343 of 438
An example in which flash memory block area EB0 is overlapped is shown in figure 14.8. 1. The RAM area to be overlapped is fixed at a 1-kbyte area in the range H'FFE000 to H'FFE3FF. 2. The flash memory area to overlap is selected by RAMER from a 1-kbyte area of the EB0 to EB3 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P1 or E1 bit in FLMCR1 to 1 does not cause a transition to program mode or erase mode. 5. A RAM area cannot be erased by execution of software in accordance with the erase algorithm. 6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM.
H'000000 Flash memory (EB0) H'0003FF H'000400 (EB1) H'0007FF H'000800 (EB2) H'000BFF H'000C00 (EB3) H'000FFF (EB3) Flash memory (EB2) On-chip RAM (Shadow of H'FFE000 to H'FFE3FF) Flash memory (EB0)
H'FFE000
On-chip RAM (1 k byte)
On-chip RAM (1 k byte)
H'FFE3FF Normal memory map RAM overlap memory map
Figure 14.8 Example of RAM Overlap Operation
Rev. 0.5, 03/03, page 344 of 438
14.8
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 14.8.1, Program/Program-Verify and section 14.8.2, Erase/Erase-Verify, respectively. 14.8.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 14.9 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to figure 14.9. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P1 bit is set to 1 is the programming time. Figure 14.9 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Rev. 0.5, 03/03, page 345 of 438
Write pulse application subroutine
Start of programming START Set SWE bit in FLMCR1 Wait (tsswe) s
Store 128-byte program data in program data area and reprogram data area
Apply Write Pulse WDT enable Set PSU1 bit in FLMCR1 Wait (tspsu) s Set P1 bit in FLMCR1 Wait (tsp) s Clear P1 bit in FLMCR1 Wait (tcp) s Clear PSU1 bit in FLMCR1 Wait (tcpsu) s
Disable WDT
Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
*7 *4
*7
Start of programming
n= 1 m= 0
*5*7
End of programming
Write 128-byte data in RAM reprogram data area consecutively to flash memory
*1
Sub-Routine-Call
*7
Apply Write pulse Set PV1 bit in FLMCR1 Wait (tspv) s
H'FF dummy write to verify address
See Note 6 for pulse width
*7
*7
Wait (tspvr) s End Sub
Increment address Note 6: Write Pulse Width Number of Writes n Write Time (tsp) s Write data = verify data? Read verify data
*7 *2
No m=1 No
nn+1
1 2 3 4 5 6 7 8 9 10 11 12 13
30 * 30 * 30 * 30 * 30 * 30 * 200 200 200 200 200 200 200
Yes 6n?
Yes Additional-programming data computation Transfer additional-programming data to additional-programming data area
Reprogram data computation
*4 *3 *4
Transfer reprogram data to reprogram data area 128-byte data verification completed?
No 998 999 1000 200 200 200
Yes Clear PV1 bit in FLMCR1 Reprogram Wait (tcpv) s 6 n? No
Note: * Use a 10 s write pulse for additional programming.
*7
RAM
Program data storage area (128 bytes)
Yes Successively write 128-byte data from additional1 programming data area in RAM to flash memory * Sub-Routine-Call Apply Write Pulse (Additional programming)
Reprogram data storage area (128 bytes)
m= 0 ? Yes Clear SWE bit in FLMCR1 Wait (tcswe) s
End of programming
No
n (N)?
*7
No
Additional-programming data storage area (128 bytes)
Yes Clear SWE bit in FLMCR1 Wait (tcswe) s
Programming failure
*7
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. 5. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 7. The wait times and value of N are shown in section 18.5, Flash Memory Characteristics.
Reprogram Data Computation Table
Original Data Verify Data Reprogram Data
Additional-Programming Data Computation Table (X) 1 0 1 1
Still in erased state; no action Comments Programming completed Programming incomplete; reprogram
(D) 0 0 1 1
(V) 0 1 0 1
Reprogram Data (X') 0 0 1 1
Verify Data Additional(V) Programming Data (Y) 0 1 0 1 0 1 1 1
Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed
Figure 14.9 Program/Program-Verify Flowchart
Rev. 0.5, 03/03, page 346 of 438
14.8.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 14.10 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E1 bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 14.8.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
Rev. 0.5, 03/03, page 347 of 438
Erase start SWE bit 1 Wait 1 s n1 Set EBR1 Enable WDT ESU1 bit 1 Wait 100 s E1 bit 1 Wait 10 s E1 bit 0 Wait 10 s ESU1 bit 0 Wait 10 s Disable WDT EV1 bit 1 Wait 20 s
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 s Read verify data No
nn+1
Increment address
Verify data = all 1s? Yes
No
Last address of block? Yes EV1 bit 0 Wait 4 s EV1 bit 0 Wait 4 s
No
All erase block erased? Yes
n 100? No
Yes
SWE bit 0 Wait 100 s End of erasing
SWE bit 0 Wait 100 s Erase failure
Figure 14.10 Erase/Erase-Verify Flowchart
Rev. 0.5, 03/03, page 348 of 438
14.9
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 14.9.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 14.9.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P1 or E1 bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00, erase protection is set for all blocks. 14.9.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction is executed during programming/erasing The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset.
Rev. 0.5, 03/03, page 349 of 438
14.10
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Hitachi 64-kbyte flash memory on-chip MCU device type (FZTAT64V5A).
14.11
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to. * Power-down mode Part of the power supply circuitry is halted, and the flash memory can be read when the LSI is operating on the subclock. * Standby mode All flash memory circuits are halted. Table 14.6 shows the correspondence between the operating modes of this LSI and the flash memory. When the flash memory returns to its normal operating state from standby mode, a period to stabilize the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 2 ms, even when the external clock is being used. Table 14.6 Flash Memory Operating States
LSI Operating State High-speed mode Medium-speed mode Sleep mode Subactive mode Subsleep mode Watch mode Software standby mode Hardware standby mode Flash Memory Operating State Normal operating mode
When PDWND = 0: Power-down mode (read-only) When PDWND = 1: Normal operating mode (read-only) Standby mode
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Section 15 Clock Pulse Generator
This LSI has an on-chip clock pulse generator that generates the system clock (), the bus master clock, internal clock, and subclock. The clock pulse generator consists of an oscillator, PLL circuit, subclock divider, clock selection circuit, medium-speed clock divider, and bus master clock selection circuit. A block diagram of the clock pulse generator is shown in figure 15.1.
LPWRCR STC1, STC0 EXTAL Clock oscillator XTAL PLL circuit ( 1, 2, 4) Clock selection circuit SUB
SCKCR SCK2 to SCK0
Mediumspeed clock divider
/2 to /32
Bus master clock selection circuit
Subclock divider (division by 128)
System clock to pin
Internal clock to peripheral modules
Bus master clock to CPU
Subclock to WDT1
Legend LPWRCR : Low-power control register SCKCR : System clock control register
Figure 15.1 Block Diagram of Clock Pulse Generator The frequency can be changed by means of the PLL circuit. Frequency changes are performed by software by settings in the low-power control register (LPWRCR) and system clock control register (SCKCR).
CPG0100A_000020020200
Rev. 0.5, 03/03, page 351 of 438
15.1
Register Descriptions
The on-chip clock pulse generator has the following registers. * System clock control register (SCKCR) * Low-power control register (LPWRCR) 15.1.1 System Clock Control Register (SCKCR)
SCKCR performs clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control.
Bit 7 Bit Name PSTOP Initial Value 0 R/W R/W Description Clock Output Disable Controls output. High-Speed Mode, Medium-Speed Mode, Subactive Mode, Sleep Mode, Subsleep Mode 0: output 1: Fixed high Software Standby Mode, Watch Mode, Direct Transition 0: Fixed high 1: Fixed high Hardware Standby Mode 0: High impedance 1: High impedance 6 to 4 3 STCS All 0 0 R/W Reserved These bits are always read as 0. Frequency Multiplication Factor Switching Mode Select Selects the operation when the PLL circuit frequency multiplication factor is changed. 0: Specified multiplication factor is valid after transition to software standby mode 1: Specified multiplication factor is valid immediately after STC1 bit and STC0 bit are rewritten
Rev. 0.5, 03/03, page 352 of 438
Bit 2 1 0
Bit Name SCK2 SCK1 SCK0
Initial Value 0 0 0
R/W R/W R/W R/W
Description System Clock Select 0 to 2 These bits select the bus master clock. 000: High-speed mode 001: Medium-speed clock is /2 010: Medium-speed clock is /4 011: Medium-speed clock is /8 100: Medium-speed clock is /16 101: Medium-speed clock is /32 11X: Setting prohibited
Legend X: Don't care
15.1.2
Low-Power Control Register (LPWRCR)
LPWRCR performs power-down mode control, subclock generation control, oscillation circuit feedback resistance control, and frequency multiplication factor setting.
Bit 7 6 5 4 Bit Name DTON LSON SUBSTP Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description See section 16.1.2, Low-Power Control Register (LPWRCR). Reserved Only write 0 to this bit. Subclock Generation Control 0: Enables subclock generation 1: Disables subclock generation 3 RFCUT 0 R/W Oscillation Circuit Feedback Resistance Control 0: When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. 1: Sets the feedback resistance OFF. Change is valid when software standby mode is entered or after software standby mode is recovered. Note: With a crystal resonator, the resonator will not operate if this bit is set to 1. 2 0 R/W Reserved Only write 0 to this bit. Rev. 0.5, 03/03, page 353 of 438
Bit 1 0
Bit Name STC1 STC0
Initial Value 0 0
R/W R/W R/W
Description Frequency Multiplication Factor The STC bits specify the frequency multiplication factor of the PLL circuit. 00: x1 01: x2 10: x4 11: Setting prohibited
15.2
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In either case, the input clock should not exceed 24 MHz. 15.2.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 15.2. Select the damping resistance Rd according to table 15.1. An AT-cut parallel-resonance crystal should be used.
CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF
Figure 15.2 Connection of Crystal Resonator (Example) Table 15.1 Damping Resistance Value
Frequency (MHz) Rd () 4 500 8 200 12 0 16 0 20 0 24 0
Rev. 0.5, 03/03, page 354 of 438
Figure 15.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 15.2.
CL XTAL L Rs EXTAL
C0
AT-cut parallel-resonance type
Figure 15.3 Crystal Resonator Equivalent Circuit Table 15.2 Crystal Resonator Characteristics
Frequency (MHz) RS max () C0 max (pF) 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7 24 40 7
15.2.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure 15.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When complementary clock is input to the XTAL pin, the external clock input should be fixed high in standby mode.
EXTAL XTAL Open
External clock input
(a) XTAL pin left open
EXTAL XTAL
External clock input
(b) Complementary clock input at XTAL pin
Figure 15.4 External Clock Input (Examples)
Rev. 0.5, 03/03, page 355 of 438
Table 15.3 shows the input conditions for the external clock. Table 15.3 External Clock Input Conditions
VCC = 5.0 V 10% Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width level Clock high pulse width level Symbol tEXL tEXH tEXr tEXf tCL tCH Min. 15 15 -- -- 0.4 80 0.4 80 Max. -- -- 5 5 0.6 -- 0.6 -- Unit ns ns ns ns tcyc ns tcyc ns 5 MHz < 5 MHz 5 MHz < 5 MHz Figure 18.2 Test Conditions Figure 15.5
tEXH
tEXL VCC 0.5
EXTAL
tEXr
tEXf
Figure 15.5 External Clock Input Timing
Rev. 0.5, 03/03, page 356 of 438
15.3
PLL Circuit
The PLL circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set by the STC0 bit and the STC1 bit in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0, the setting becomes valid after a transition to software standby mode. The transition time count is performed in accordance with the setting of bits STS0 to STS2 in SBYCR. For details on SBYCR, refer to section 16.1.1, Standby Control Register (SBYCR). 1. The initial PLL circuit multiplication factor is 1. 2. STS0 to STS2 are set to give the specified transition time. 3. The target value is set in STC0 and STC1, and a transition is made to software standby mode. 4. The clock pulse generator stops and the value set in STC0 and STC1 becomes valid. 5. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS0 to STS2. 6. After the set transition time has elapsed, this LSI resumes operation using the target multiplication factor.
15.4
Subclock Divider
The subclock divider divides the clock generated by the oscillator by 128 to generate a subclock. When using the subclock as a system clock, adjustment by software is needed.
15.5
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32.
15.6
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the clock supplied to the bus master by setting the bits SCK 2 to 0 in SCKCR. The bus master clock can be selected from high-speed mode, or medium-speed clocks (/2, /4, /8, /16, /32).
Rev. 0.5, 03/03, page 357 of 438
15.7
15.7.1
Usage Notes
Note on Crystal Resonator
As various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 15.7.2 Note on Board Design
When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator circuit, as shown in figure 15.6. This is to prevent induction from interfering with correct oscillation.
Avoid CL2 Signal A Signal B This LSI XTAL EXTAL CL1
Figure 15.6 Note on Board Design of Oscillator Circuit Figure 15.7 shows external circuitry recommended to be provided around the PLL circuit. Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Separate PLLVcL and PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert bypass capacitors CB close to the pins.
Rev. 0.5, 03/03, page 358 of 438
R1 : 3 k
C1 : 470 pF
PLLCAP PLLVCL
CB : 0.1 F
PLLVSS VCL VCC
CB : 0.1 F* CB : 0.1 F
VSS (Values are preliminary recommended values.) Note: * CB are laminated ceramic.
Figure 15.7 External Circuitry Recommended for PLL Circuit
Rev. 0.5, 03/03, page 359 of 438
Rev. 0.5, 03/03, page 360 of 438
Section 16 Power-Down Modes
In addition to the normal program execution state, this LSI has eight power-down modes in which operation of the CPU and oscillator is halted and power consumption is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on. This LSI's operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Subactive mode (4) Sleep mode (5) Subsleep mode (6) Watch mode (7) Module stop mode (8) Software standby mode (9) Hardware standby mode (2) to (9) are power-down modes. Sleep and subsleep modes are CPU states, medium-speed mode is a CPU and bus master state, subactive mode is a CPU, bus master, and on-chip peripheral function state, and module stop mode is an on-chip peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI is in high-speed mode or module stop mode. Figure 16.1 shows a mode transition. Table 16.1 shows the conditions of transition between modes when executing the SLEEP instruction and the state after transition back from low power mode due to an interrupt. Table 16.2 shows the internal state of the LSI in each mode.
Rev. 0.5, 03/03, page 361 of 438
Program-halted state pin = Low Hardware standby mode
Reset state
pin = High, pin = Low
pin = High Program execution state Sleep command High-speed mode (main clock) SSBY = 0 Sleep mode (main clock)
All interrupts *3
SCK2 to SCK0 = 0
SCK2 to SCK0 0
Sleep command
SSBY = 1 Software standby mode
Medium-speed mode (main clock)
External interrupt *4 Sleep command
Sleep command SSBY = 1, PSS = 1, DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to STS0), clock switching exception processing
Sleep command SSBY = 1, PSS = 1, DTON = 1, LSON = 1 Clock switching exception processing
SSBY = 1 PSS = 1, DTON = 0 Interrupt*1, LSON bit = 0 Sleep command Interrupt*1, LSON bit = 1 Sleep command Interrupts *2 Watch mode (subclock)
SSBY = 0 PSS = 1, LSON = 1 Subsleep mode (subclock)
Subactive mode (subclock)
: Transition after exception processing Notes : *1 *2 *3 *4 NMI, IRQ0 to IRQ5, and WDT_1 interrupts NMI, IRQ0 to IRQ5, WDT_0, and WDT_1 interrupts All interrupts NMI and IRQ0 to IRQ5
: Power-down mode
When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. From any state except hardware standby mode, a transition to the reset state occurs when is driven low. From any state, a transition to hardware standby mode occurs when is driven low. Always select high-speed mode before making a transition to watch mode or subactive mode.
Figure 16.1 Mode Transition Diagram
Rev. 0.5, 03/03, page 362 of 438
Table 16.1 Power-Down Mode Transition Conditions
PreTransition State Highspeed/ Mediumspeed Status of Control Bit at Transition SSBY 0 0 1 1 1 1 1 1 Subactive 0 0 0 1 1 1 1 1 Legend x: Don't care : Setting prohibited PSS x x 0 0 1 1 1 1 0 1 1 0 1 1 1 1 LSON 0 1 0 1 0 1 0 1 x 0 1 x 0 1 0 1 DTON x x x x 0 0 1 1 x x x x 0 0 1 1 State after Transition Invoked by SLEEP Instruction Sleep Software standby Watch Watch Subactive Subsleep Watch Watch High-speed State after Transition back from PowerDown Mode Invoked by Interrupt High-speed/Mediumspeed High-speed/Mediumspeed High-speed Subactive Subactive High-speed Subactive
Rev. 0.5, 03/03, page 363 of 438
Table 16.2 LSI Internal States in Each Mode
MediumFunction System clock pulse generator CPU Instructions Functioning Registers Mediumspeed operation Halted (retained) High/ mediumspeed operation External interrupts NMI IRQ0 to IRQ5 Peripheral WDT_0 functions WDT_1 Functioning Functioning Functioning Functioning Functioning Functioning Halted (retained) Subclock operation I/O Functioning Functioning Functioning Functioning Retained Subclock operation Subclock operation Functioning Subclock operation Subclock operation Retained Halted (retained) Halted (retained) Retained Halted (reset) Halted (reset) High impedance TPU Functioning Functioning Functioning Halted (retained) SCI HCAN A/D RAM Functioning Mediumspeed operation Functioning Functioning Retained Functioning Retained Retained Retained Functioning Functioning Functioning Halted (reset) Halted (retained) Halted (reset) Halted (retained) Halted (reset) Halted (retained) Halted (reset) Halted (retained) Halted (reset) Halted (reset) Halted (reset) Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Halted (retained) Subclock operation Halted (retained) Halted (retained) Halted (undefined) High-Speed Speed Functioning Functioning Sleep Functioning Module Stop Functioning Watch Halted Subactive Halted Subsleep Halted Software Standby Halted Hardware Standby Halted
Notes: "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained).
Rev. 0.5, 03/03, page 364 of 438
16.1
Register Descriptions
Registers related to the power down mode are shown below. For details on the system clock control register (SCKCR), refer to section 15.1.1, System Clock Control Register (SCKCR). * System clock control register (SCKCR) * Standby control register (SBYCR) * Low-power control register (LPWRCR) * Module stop control register A (MSTPCRA) * Module stop control register B (MSTPCRB) * Module stop control register C (MSTPCRC) 16.1.1 Standby Control Register (SBYCR)
SBYCR performs software standby mode control.
Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit determines the operating mode when a transition is made to power-down mode after executing the SLEEP instruction according to the combination of the other control bits. 0: Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to subsleep mode when the SLEEP instruction is executed in subactive mode. 1: Shifts to software standby mode, subactive mode, or watch mode* when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in subactive mode. Note: When entering watch mode or subactive mode, the operating mode must be set to high-speed mode.
Rev. 0.5, 03/03, page 365 of 438
Bit 6 5 4
Bit Name STS2 STS1 STS0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Standby Timer Select 0 to 2 These bits select the MCU wait time for clock stabilization when software standby mode, watch mode, or subactive mode is cancelled by an external interrupt. With a crystal oscillator (table 16.3), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, select a wait time of 2 ms or more. 000: Standby time = 8192 states 001: Standby time = 16384 states 010: Standby time = 32768 states 011: Standby time = 65536 states 100: Standby time = 131072 states 101: Standby time = 262144 states 110: Reserved 111: Standby time = 16 states
3 2 to 0

1 All 0
R/W
Reserved Only 1 should be written to this bit. Reserved These bits are always read as 0 and cannot be modified.
Rev. 0.5, 03/03, page 366 of 438
16.1.2
Low-Power Control Register (LPWRCR)
LPWRCR performs power-down mode control, subclock generation control, oscillation circuit feedback resistance control, and frequency multiplication factor setting.
Bit 7 Bit Name DTON Initial Value 0 R/W R/W Description Direct Transition ON Flag 0: When the SLEEP instruction is executed in highspeed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in subactive mode, operation shifts to subsleep mode or watch mode. 1: When the SLEEP instruction is executed in highspeed mode or medium-speed mode, operation shifts directly to subactive mode*, or shifts to sleep mode or software standby mode. When the SLEEP instruction is executed in subactive mode, operation shifts directly to high-speed mode, or shifts to subsleep mode. 6 LSON 0 R/W Low-Speed ON Flag 0: When the SLEEP instruction is executed in highspeed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in subactive mode, operation shifts to watch mode or shifts directly to high-speed mode. Operation shifts to high-speed mode when watch mode is cancelled. 1: When the SLEEP instruction is executed in highspeed mode, operation shifts to watch mode or subactive mode*. When the SLEEP instruction is executed in sub-active mode, operation shifts to subsleep mode or watch mode. Operation shifts to subactive mode when watch mode is cancelled. 5 0 R/W Reserved This bit can be read from and written to. However, do not write 1 to this bit. 4 SUBSTP 0 R/W Subclock Generation Control 0: Enables subclock generation 1: Disables subclock generation
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Bit 3
Bit Name RFCUT
Initial Value 0
R/W R/W
Description Oscillation Circuit Feedback Resistance Control 0: When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. 1: Sets the feedback resistance OFF. Change is valid when software standby mode is entered or after software standby mode is recovered. Note: With a crystal resonator, the resonator will not operate if this bit is set to 1.
2
0
R/W
Reserved This bit can be read from and written to. However, do not write 1 to this bit.
1 0
STC1 STC0
0 0
R/W R/W
Frequency Multiplication Factor Setting These bits specify the frequency multiplication factor of the PLL circuit. 00: x1 01: x2 10: x4 11: Setting prohibited
Note:
*
Always set high-speed mode when shifting to watch mode or subactive mode.
16.1.3
Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)
MSTPCR performs module stop mode control. Setting a bit to 1 causes the corresponding module to enter module stop mode. Clearing the bit to 0 clears the module stop mode.
Rev. 0.5, 03/03, page 368 of 438
MSTPCRA
Bit 7 6 5 4 3 2 1 0 Bit Name MSTPA7* MSTPA6* MSTPA5 MSTPA4* MSTPA3* MSTPA2* MSTPA1 MSTPA0* Initial Value 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W A/D converter 16-bit timer pulse unit (TPU) Module
MSTPCRB
Bit 7 6 5 4 3 2 1 0 Bit Name MSTPB7 MSTPB6 MSTPB5 MSTPB4* MSTPB3* MSTPB2* MSTPB1* MSTPB0* Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Module Serial communication interface_0 (SCI_0) Serial communication interface_1 (SCI_1) Serial communication interface_2 (SCI_2)
Rev. 0.5, 03/03, page 369 of 438
MSTPCRC
Bit 7 6 5 4 3 2 1 0 Note: Bit Name MSTPC7* MSTPC6* MSTPC5* MSTPC4* MSTPC3 MSTPC2* MSTPC1* MSTPC0* * Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Hitachi Controller Area Network (HCAN) Module
MSTPA7 and MSTPA6 are readable/writable bits with an initial value of 0 and should always be written with 0. MSTPA4 to MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC4, and MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1.
16.2
Medium-Speed Mode
When the SCK0 to SCK2 bits in SCKCR are set to 1, the operating mode changes to mediumspeed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK0 to SCK2 bits. On-chip peripheral modules other than bus masters always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK0 to SCK2 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer.
Rev. 0.5, 03/03, page 370 of 438
When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 16.2 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode , peripheral module clock
Bus master clock
Internal address bus
SCKCR
SCKCR
Internal write signal
Figure 16.2 Medium-Speed Mode Transition and Clearance Timing
16.3
16.3.1
Sleep Mode
Transition to Sleep Mode
If SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops, however the contents of the CPU's internal registers are retained. Other peripheral modules do not stop. 16.3.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt, or signals at the RES, or STBY pins. * Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or if interrupts other than NMI are masked by the CPU. * Exiting Sleep Mode by RES pin: Setting the RES pin Low selects the reset state. After the stipulated reset input duration, driving the RES pin High restart the CPU performing reset exception processing. * Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven low, a transition is made to hardware standby mode.
Rev. 0.5, 03/03, page 371 of 438
16.4
16.4.1
Software Standby Mode
Transition to Software Standby Mode
A transition is made to software standby mode if the SLEEP instruction is executed when the SBYCR SSBY bit is set to 1. In this mode, the CPU, on-chip peripheral modules, and oscillator, all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral modules other than the SCI, A/D converter, and the states of I/O ports, are retained. In this mode, the oscillator stops, and therefore power consumption is significantly reduced. 16.4.2 Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by means of the RES pin or STBY pin. * Clearing with an interrupt When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and after the time set in bits STS0 to STS2 in SBYCR has elapsed, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side. * Clearing with the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. * Clearing with the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev. 0.5, 03/03, page 372 of 438
16.4.3
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below. * Using a Crystal Oscillator Set bits STS0 to STS2 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 16.3 shows the standby times for different operating frequencies and settings of bits STS0 to STS2. * Using an External Clock The PLL circuit requires a time for stabilization. Set bits STS0 to STS2 so that the standby time is at least 2 ms. Table 16.3 Oscillation Stabilization Time Settings
24 20 16 12 10 8 6 4 STS2 STS1 STS0 Standby Time MHz MHz MHz MHz MHz MHz MHz MHz Unit 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states* 0.34 0.41 0.51 0.68 0.8 0.68 0.82 1.0 1.4 2.7 5.5 0.7 1.6 3.3 6.6 0.8 2.0 4.1 8.2 1.0 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 8.2 ms
10.9 16.4
10.9 13.1 16.4 21.8 32.8 1.3 1.6 2.0 1.7 4.0 s
10.9 13.1 16.4 21.8 26.2 32.8 43.6 65.6
: Recommended time setting Note: * Cannot be set.
16.4.4
Software Standby Mode Application Example
Figure 16.3 shows an example in which a transition is made to software standby mode at a falling edge on the NMI pin, and software standby mode is cleared at a rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin.
Rev. 0.5, 03/03, page 373 of 438
Oscillator
NMI
NMIEG
SSBY
NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction
NMI exception handling Oscillation stabilization time tOSC2
Figure 16.3 Software Standby Mode Application Example
16.5
16.5.1
Hardware Standby Mode
Transition to Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD0 to MD2) while this LSI is in hardware standby mode.
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16.5.2
Clearing Hardware Standby Mode
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms--the oscillation stabilization time--when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 16.5.3 Hardware Standby Mode Timings
Timing of Transition to Hardware Standby Mode 1. To retain RAM contents with the RAME bit set to 1 in SYSCR Drive the RES signal low at least 10 states before the STBY signal goes low, as shown in figure 16.4. After STBY has gone low, RES has to wait for at least 0 ns before becoming high.
t110tcyc
t20ns
Figure 16.4 Timing of Transition to Hardware Standby Mode 2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained RES does not have to be driven low as in the above case. Timing of Recovery from Hardware Standby Mode Drive the RES signal low approximately 100 ns or more before STBY goes high to execute a power-on reset.
t100ns
tOSC1
Figure 16.5 Timing of Recovery from Hardware Standby Mode
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16.6
Module Stop Mode
Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI*, HCAN, and A/D converter are retained. After reset clearance, all modules are in module stop mode. When an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. Note: The internal states of some SCI registers are retained.
16.7
16.7.1
Watch Mode
Transition to Watch Mode
CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or subactive mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR_1 (WDT_1) = 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped. The contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral modules other than the SCI, HCAN, and A/D converter, and the states of I/O ports, are retained. 16.7.2 Canceling Watch Mode
Watch mode is canceled by any interrupt (WOVI1 interrupt, NMI pin, or IRQ0 to IRQ5 pin), or signals at the RES, or STBY pin. Canceling Watch Mode by Interrupt: When an interrupt occurs, watch mode is canceled and a transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR = 0 or to subactive mode when the LSON bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits and interrupt exception processing starts after the time set in the STS2 to STS0 bits of SBYCR has elapsed. In case of an IRQ0 to IRQ5 interrupt, watch mode is not canceled if the corresponding enable bit has been cleared to 0. In case of the interrupt
Rev. 0.5, 03/03, page 376 of 438
from the on-chip peripheral modules, if the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU, watch mode is not canceled. For the setting of the oscillation stabilization time when making a transition from watch mode to high-speed mode, see section 16.4.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode. Canceling Watch Mode by RES pin: For canceling watch mode by the RES pin, see section 16.4.2, Clearing Software Standby Mode. Canceling Watch Mode by STBY pin: When the STBY pin is driven low, a transition is made to hardware standby mode.
16.8
16.8.1
Subsleep Mode
Transition to Subsleep Mode
When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR = 0, the LSON bit in LPWRCR = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, CPU operation shifts to subsleep mode. In subsleep mode, the CPU is stopped and peripheral modules other than WDT_0 and WDT_1 are also stopped. The contents of the CPU's internal registers, on-chip RAM data, and the states of onchip peripheral modules other than the SCI, HCAN, and A/D converter, and the states of I/O ports, are retained. 16.8.2 Canceling Subsleep Mode
Subsleep mode is canceled by any interrupt (WOVI0 or WOVI1 interrupt, NMI pin, or IRQ0 to IRQ5 pin), or signals at the RES or STBY pin. Canceling Subsleep Mode by Interrupt: When an interrupt occurs, subsleep mode is canceled and interrupt exception processing starts. In case of an IRQ0 to IRQ5 interrupt, subsleep mode is not canceled if the corresponding enable bit has been cleared to 0. In case of the interrupt from the on-chip peripheral modules, if the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU, subsleep mode is not canceled. Canceling Subsleep Mode by RES pin: For canceling subsleep mode by the RES pin, see section 16.4.2, Clearing Software Standby Mode. Canceling Subsleep Mode by STBY pin: When the STBY pin is driven low, a transition is made to hardware standby mode.
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16.9
16.9.1
Subactive Mode
Transition to Subactive Mode
CPU operation makes a transition to subactive mode when the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a transition is made to subactive mode. And if an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at low speed on the subclock, and the program is executed one after another. Peripheral modules other than WDT_0 and WDT_1 are also stopped. When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SCKCR must be set to 0. 16.9.2 Canceling Subactive Mode
Subactive mode is canceled by the SLEEP instruction or signals at the RES or STBY pin. Canceling Subactive Mode by SLEEP Instruction: When the SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR_1 (WDT_1) = 1, subactive mode is canceled and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR = 0, the LSON bit in LPWRCR = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 0, and the PSS bit in TCSR_1 (WDT_1) = 1, a direct transition is made to highspeed mode (SCK0 to SCK2 are all 0). Canceling Subactive Mode by RES pin: For canceling subactive mode by the RES pin, see section 16.4.2, Clearing Software Standby Mode. Canceling Subactive Mode by STBY pin: When the STBY pin is driven low, a transition is made to hardware standby mode.
16.10
Direct Transitions
There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution in shifting between high-speed and subactive modes. Direct transitions are enabled by setting the DTON bit in LPWRCR to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception processing starts.
Rev. 0.5, 03/03, page 378 of 438
16.10.1 Direct Transitions from High-Speed Mode to Subactive Mode Execute the SLEEP instruction in high-speed mode with the SSBY bit in SBYCR = 1, the LSON bit in LPWRCR= 1, the DTON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, to make a direct transition to subactive mode. 16.10.2 Direct Transitions from Subactive Mode to High-Speed Mode Execute the SLEEP instruction in subactive mode with the SSBY bit in SBYCR = 1, the LSON bit in LPWRCR = 0, the DTON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, to make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits of SBYCR has elapsed.
16.11
Clock Output Disabling Function
The output of the clock can be controlled by means of the PSTOP bit in SCKCR and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 16.4 shows the state of the pin in each processing state. Table 16.4 Pin State in Each Processing State
Register Settings High-Speed Mode, MediumSpeed Mode High impedance output Fixed high Software Standby Mode, Watch Mode, Direct Transitions High impedance Fixed high Fixed high
DDR 0 1 1
PSTOP X 0 1
Subactive Mode High impedance SUB output Fixed high
Sleep Mode, Subsleep Mode High impedance output Fixed high
Hardware Standby Mode High impedance High impedance High impedance
Legend X: Don't care
Rev. 0.5, 03/03, page 379 of 438
16.12
Usage Notes
16.12.1 I/O Port Status In software standby mode, I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 16.12.2 Current Consumption during Oscillation Stabilization Wait Period Current consumption increases during the oscillation stabilization wait period. 16.12.3 On-Chip Peripheral Module Interrupt The on-chip peripheral module (TPU), that halts in subactive mode, cannot cancel that interrupt in subactive mode. Thus, if a transition is made to subactive mode via watch mode when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before executing the SLEEP instruction, then entering watch mode. 16.12.4 Writing to MSTPCR MSTPCR should only be written to by the CPU.
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Section 17 List of Registers
The address list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) * Registers are listed from the lower allocation addresses. * Registers are classified by functional modules. * The access size is indicated. 2. Register bits * Bit configurations of the registers are described in the same order as the register addresses. * Reserved bits are indicated by in the bit name column. * No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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17.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Register Name Master control register General status register Bit configuration register Mailbox configuration register Transmit wait register Transmit wait cancel register Transmit acknowledge register Abort acknowledge register Receive complete register Remote request register Interrupt register Mailbox interrupt mask register Interrupt mask register Receive error counter Transmit error counter Unread message status register Local acceptance filter mask L Local acceptance filter mask H Message control 0[1] Message control 0[2] Message control 0[3] Message control 0[4] Message control 0[5] Message control 0[6] Message control 0[7] Message control 0[8] Message control 1[1] Abbreviation MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] Bit No. 8 8 16 16 16 16 16 16 16 16 16 16 16 8 8 16 16 16 8 8 8 8 8 8 8 8 8 Data Address* Module Width H'F800 H'F801 H'F802 H'F804 H'F806 H'F808 H'F80A H'F80C H'F80E H'F810 H'F812 H'F814 H'F816 H'F818 H'F819 H'F81A H'F81C H'F81E H'F820 H'F821 H'F822 H'F823 H'F824 H'F825 H'F826 H'F827 H'F828 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access State 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Rev. 0.5, 03/03, page 382 of 438
Register Name Message control 1[2] Message control 1[3] Message control 1[4] Message control 1[5] Message control 1[6] Message control 1[7] Message control 1[8] Message control 2[1] Message control 2[2] Message control 2[3] Message control 2[4] Message control 2[5] Message control 2[6] Message control 2[7] Message control 2[8] Message control 3[1] Message control 3[2] Message control 3[3] Message control 3[4] Message control 3[5] Message control 3[6] Message control 3[7] Message control 3[8] Message control 4[1] Message control 4[2] Message control 4[3] Message control 4[4] Message control 4[5] Message control 4[6] Message control 4[7] Message control 4[8] Message control 5[1] Message control 5[2]
Abbreviation MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] MC5[1] MC5[2]
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'F829 H'F82A H'F82B H'F82C H'F82D H'F82E H'F82F H'F830 H'F831 H'F832 H'F833 H'F834 H'F835 H'F836 H'F837 H'F838 H'F839 H'F83A H'F83B H'F83C H'F83D H'F83E H'F83F H'F840 H'F841 H'F842 H'F843 H'F844 H'F845 H'F846 H'F847 H'F848 H'F849 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access State 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Rev. 0.5, 03/03, page 383 of 438
Register Name Message control 5[3] Message control 5[4] Message control 5[5] Message control 5[6] Message control 5[7] Message control 5[8] Message control 6[1] Message control 6[2] Message control 6[3] Message control 6[4] Message control 6[5] Message control 6[6] Message control 6[7] Message control 6[8] Message control 7[1] Message control 7[2] Message control 7[3] Message control 7[4] Message control 7[5] Message control 7[6] Message control 7[7] Message control 7[8] Message control 8[1] Message control 8[2] Message control 8[3] Message control 8[4] Message control 8[5] Message control 8[6] Message control 8[7] Message control 8[8] Message control 9[1] Message control 9[2] Message control 9[3]
Abbreviation MC5[3] MC5[4] MC5[5] MC5[6] MC5[7] MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] MC8[7] MC8[8] MC9[1] MC9[2] MC9[3]
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'F84A H'F84B H'F84C H'F84D H'F84E H'F84F H'F850 H'F851 H'F852 H'F853 H'F854 H'F855 H'F856 H'F857 H'F858 H'F859 H'F85A H'F85B H'F85C H'F85D H'F85E H'F85F H'F860 H'F861 H'F862 H'F863 H'F864 H'F865 H'F866 H'F867 H'F868 H'F869 H'F86A HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access State 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
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Register Name Message control 9[4] Message control 9[5] Message control 9[6] Message control 9[7] Message control 9[8] Message control 10[1] Message control 10[2] Message control 10[3] Message control 10[4] Message control 10[5] Message control 10[6] Message control 10[7] Message control 10[8] Message control 11[1] Message control 11[2] Message control 11[3] Message control 11[4] Message control 11[5] Message control 11[6] Message control 11[7] Message control 11[8] Message control 12[1] Message control 12[2] Message control 12[3] Message control 12[4] Message control 12[5] Message control 12[6] Message control 12[7] Message control 12[8] Message control 13[1] Message control 13[2] Message control 13[3] Message control 13[4]
Abbreviation MC9[4] MC9[5] MC9[6] MC9[7] MC9[8] MC10[1] MC10[2] MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4]
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'F86B H'F86C H'F86D H'F86E H'F86F H'F870 H'F871 H'F872 H'F873 H'F874 H'F875 H'F876 H'F877 H'F878 H'F879 H'F87A H'F87B H'F87C H'F87D H'F87E H'F87F H'F880 H'F881 H'F882 H'F883 H'F884 H'F885 H'F886 H'F887 H'F888 H'F889 H'F88A H'F88B HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access State 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
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Register Name Message control 13[5] Message control 13[6] Message control 13[7] Message control 13[8] Message control 14[1] Message control 14[2] Message control 14[3] Message control 14[4] Message control 14[5] Message control 14[6] Message control 14[7] Message control 14[8] Message control 15[1] Message control 15[2] Message control 15[3] Message control 15[4] Message control 15[5] Message control 15[6] Message control 15[7] Message control 15[8] Message data 0[1] Message data 0[2] Message data 0[3] Message data 0[4] Message data 0[5] Message data 0[6] Message data 0[7] Message data 0[8] Message data 1[1] Message data 1[2] Message data 1[3] Message data 1[4] Message data 1[5]
Abbreviation MC13[5] MC13[6] MC13[7] MC13[8] MC14[1] MC14[2] MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD0[1] MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] MD1[2] MD1[3] MD1[4] MD1[5]
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'F88C H'F88D H'F88E H'F88F H'F890 H'F891 H'F892 H'F893 H'F894 H'F895 H'F896 H'F897 H'F898 H'F899 H'F89A H'F89B H'F89C H'F89D H'F89E H'F89F H'F8B0 H'F8B1 H'F8B2 H'F8B3 H'F8B4 H'F8B5 H'F8B6 H'F8B7 H'F8B8 H'F8B9 H'F8BA H'F8BB H'F8BC HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access State 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Rev. 0.5, 03/03, page 386 of 438
Register Name Message data 1[6] Message data 1[7] Message data 1[8] Message data 2[1] Message data 2[2] Message data 2[3] Message data 2[4] Message data 2[5] Message data 2[6] Message data 2[7] Message data 2[8] Message data 3[1] Message data 3[2] Message data 3[3] Message data 3[4] Message data 3[5] Message data 3[6] Message data 3[7] Message data 3[8] Message data 4[1] Message data 4[2] Message data 4[3] Message data 4[4] Message data 4[5] Message data 4[6] Message data 4[7] Message data 4[8] Message data 5[1] Message data 5[2] Message data 5[3] Message data 5[4] Message data 5[5] Message data 5[6]
Abbreviation MD1[6] MD1[7] MD1[8] MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] MD4[1] MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6]
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'F8BD H'F8BE H'F8BF H'F8C0 H'F8C1 H'F8C2 H'F8C3 H'F8C4 H'F8C5 H'F8C6 H'F8C7 H'F8C8 H'F8C9 H'F8CA H'F8CB H'F8CC H'F8CD H'F8CE H'F8CF H'F8D0 H'F8D1 H'F8D2 H'F8D3 H'F8D4 H'F8D5 H'F8D6 H'F8D7 H'F8D8 H'F8D9 H'F8DA H'F8DB H'F8DC H'F8DD HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access State 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Rev. 0.5, 03/03, page 387 of 438
Register Name Message data 5[7] Message data 5[8] Message data 6[1] Message data 6[2] Message data 6[3] Message data 6[4] Message data 6[5] Message data 6[6] Message data 6[7] Message data 6[8] Message data 7[1] Message data 7[2] Message data 7[3] Message data 7[4] Message data 7[5] Message data 7[6] Message data 7[7] Message data 7[8] Message data 8[1] Message data 8[2] Message data 8[3] Message data 8[4] Message data 8[5] Message data 8[6] Message data 8[7] Message data 8[8] Message data 9[1] Message data 9[2] Message data 9[3] Message data 9[4] Message data 9[5] Message data 9[6] Message data 9[7] Message data 9[8] Rev. 0.5, 03/03, page 388 of 438
Abbreviation MD5[7] MD5[8] MD6[1] MD6[2] MD6[3] MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6] MD7[7] MD7[8] MD8[1] MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8]
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'F8DE H'F8DF H'F8E0 H'F8E1 H'F8E2 H'F8E3 H'F8E4 H'F8E5 H'F8E6 H'F8E7 H'F8E8 H'F8E9 H'F8EA H'F8EB H'F8EC H'F8ED H'F8EE H'F8EF H'F8F0 H'F8F1 H'F8F2 H'F8F3 H'F8F4 H'F8F5 H'F8F6 H'F8F7 H'F8F8 H'F8F9 H'F8FA H'F8FB H'F8FC H'F8FD H'F8FE H'F8FF HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access State 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Register Name Message data 10[1] Message data 10[2] Message data 10[3] Message data 10[4] Message data 10[5] Message data 10[6] Message data 10[7] Message data 10[8] Message data 11[1] Message data 11[2] Message data 11[3] Message data 11[4] Message data 11[5] Message data 11[6] Message data 11[7] Message data 11[8] Message data 12[1] Message data 12[2] Message data 12[3] Message data 12[4] Message data 12[5] Message data 12[6] Message data 12[7] Message data 12[8] Message data 13[1] Message data 13[2] Message data 13[3] Message data 13[4] Message data 13[5] Message data 13[6] Message data 13[7] Message data 13[8] Message data 14[1]
Abbreviation MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4] MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1]
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'F900 H'F901 H'F902 H'F903 H'F904 H'F905 H'F906 H'F907 H'F908 H'F909 H'F90A H'F90B H'F90C H'F90D H'F90E H'F90F H'F910 H'F911 H'F912 H'F913 H'F914 H'F915 H'F916 H'F917 H'F918 H'F919 H'F91A H'F91B H'F91C H'F91D H'F91E H'F91F H'F920 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access State 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Rev. 0.5, 03/03, page 389 of 438
Register Name Message data 14[2] Message data 14[3] Message data 14[4] Message data 14[5] Message data 14[6] Message data 14[7] Message data 14[8] Message data 15[1] Message data 15[2] Message data 15[3] Message data 15[4] Message data 15[5] Message data 15[6] Message data 15[7] Message data 15[8] HCAN monitor register Standby control register System control register System clock control register Mode control register Module stop control register A Module stop control register B Module stop control register C Low-power control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Port 1 data direction register Port A data direction register Port B data direction register Port C data direction register Port D data direction register
Abbreviation MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] MD14[7] MD14[8] MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8]
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'F921 H'F922 H'F923 H'F924 H'F925 H'F926 H'F927 H'F928 H'F929 H'F92A H'F92B H'F92C H'F92D H'F92E H'F92F H'FA00 H'FDE4 H'FDE5 H'FDE6 H'FDE7 H'FDE8 H'FDE9 H'FDEA H'FDEC H'FE12 H'FE13 H'FE14 H'FE15 H'FE30 H'FE39 H'FE3A H'FE3B H'FE3C HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access State 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
HCANMON 8 SBYCR SYSCR SCKCR MDCR 8 8 8 8
SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 INT INT INT INT PORT PORT PORT PORT PORT 8 8 8 8 8 8 8 8 8
MSTPCRA 8 MSTPCRB 8 MSTPCRC 8 LPWRCR ISCRH ISCRL IER ISR P1DDR PADDR PBDDR PCDDR PDDDR 8 8 8 8 8 8 8 8 8 8
Rev. 0.5, 03/03, page 390 of 438
Register Name Port F data direction register
Abbreviation Bit No. PFDDR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16
Data Address* Module Width H'FE3E H'FE40 H'FE41 H'FE42 H'FE43 H'FE47 H'FE48 H'FE49 H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE98 H'FE9A H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 PORT PORT PORT PORT PORT PORT PORT PORT TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access State 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Port A pull-up MOS control register PAPCR Port B pull-up MOS control register PBPCR Port C pull-up MOS control register PCPCR Port D pull-up MOS control register PDPCR Port A open drain control register Port B open drain control register Port C open drain control register Timer control register_3 Timer mode register_3 Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter _3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3 Timer control register_4 Timer mode register_4 Timer I/O control register_4 Timer interrupt enable register_4 Timer status register_4 Timer counter_4 Timer general register A_4 Timer general register B_4 Timer control register_5 Timer mode register_5 Timer I/O control register_5 Timer interrupt enable register_5 Timer status register_5 Timer counter_5 PAODR PBODR PCODR TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5
Rev. 0.5, 03/03, page 391 of 438
Register Name Timer general register A_5 Timer general register B_5 Timer start register Timer synchro register Interrupt priority register A Interrupt priority register B Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register J Interrupt priority register K Interrupt priority register M RAM emulation register Port 1 data register Port A data register Port B data register Port C data register Port D data register Port F data register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0
Abbreviation TGRA_5 TGRB_5 TSTR TSYR IPRA IPRB IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRM RAMER P1DR PADR PBDR PCDR PDDR PFDR TCR_0 TMDR_0 TIORH_0 TIORL_0
Bit No. 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16
Data Address* Module Width H'FEA8 H'FEAA H'FEB0 H'FEB1 H'FEC0 H'FEC1 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC9 H'FECA H'FECC H'FEDB H'FF00 H'FF09 H'FF0A H'FF0B H'FF0C H'FF0E H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF18 H'FF1A H'FF1C TPU_5 TPU_5 16 16
Access State 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
TPU 16 common TPU 16 common INT INT INT INT INT INT INT INT INT INT ROM PORT PORT PORT PORT PORT PORT TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16
Timer interrupt enable register_0 TIER_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0
Rev. 0.5, 03/03, page 392 of 438
Register Name Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1
Abbreviation TGRD_0 TCR_1 TMDR_1 TIOR_1
Bit No. 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'FF1E H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF28 H'FF2A H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 H'FF36 H'FF38 H'FF3A H'FF74 H'FF75 H'FF77 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 TPU_0 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 WDT_0 WDT_0 WDT_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8
Access State 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Timer interrupt enable register_1 TIER_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2
Timer interrupt enable register_2 TIER_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Timer control/status register_0 Timer counter_0 Reset control/status register Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCSR_0 TCNT_0 RSTCSR SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1
Rev. 0.5, 03/03, page 393 of 438
Register Name Smart card mode register_1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Timer control/status register_1 Timer counter_1
Abbreviation SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Data Address* Module Width H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFA2 H'FFA3 H'FFA8 H'FFA9 H'FFAA H'FFAC H'FFB0 H'FFB3 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBE SCI_1 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D WDT_1 WDT_1 ROM ROM ROM ROM PORT PORT PORT PORT PORT PORT PORT PORT 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8
Access State 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Flash memory control register 1 FLMCR1 Flash memory control register 2 FLMCR2 Erase block register 1 Flash memory power control register Port 1 register Port 4 register Port 9 register Port A register Port B register Port C register Port D register Port F register EBR1 FLPWCR PORT1 PORT4 PORT9 PORTA PORTB PORTC PORTD PORTF
Note: Lower 16 bits of the address. Rev. 0.5, 03/03, page 394 of 438
17.2
Register Bits
Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines.
Register Name MCR GSR BCR Bit 7 MCR7 -- BCR7 BCR15 MBCR MBCR7 MBCR15 TXPR TXPR7 TXPR15 TXCR TXCR7 TXCR15 TXACK TXACK7 TXACK15 ABACK ABACK7 ABACK15 RXPR RXPR7 RXPR15 RFPR RFPR7 RFPR15 IRR IRR7 -- MBIMR MBIMR7 MBIMR15 IMR IMR7 -- REC TEC UMSR Bit 7 Bit 7 UMSR7 UMSR15 LAFML LAFML7 LAFML15 LAFMH LAFMH7 LAFMH15 MC0[1] MC0[2] MC0[3] MC0[4] -- -- -- -- Bit 6 -- -- BCR6 BCR14 MBCR6 MBCR14 TXPR6 TXPR14 TXCR6 TXCR14 TXACK6 TXACK14 ABACK6 ABACK14 RXPR6 RXPR14 RFPR6 RFPR14 IRR6 -- MBIMR6 MBIMR14 IMR6 -- Bit 6 Bit 6 UMSR6 UMSR14 LAFML6 LAFML14 LAFMH6 LAFMH14 -- -- -- -- Bit 5 MCR5 -- BCR5 BCR13 MBCR5 MBCR13 TXPR5 TXPR13 TXCR5 TXCR13 TXACK5 TXACK13 ABACK5 ABACK13 RXPR5 RXPR13 RFPR5 RFPR13 IRR5 -- MBIMR5 MBIMR13 IMR5 -- Bit 5 Bit 5 UMSR5 UMSR13 LAFML5 LAFML13 LAFMH5 LAFMH13 -- -- -- -- Bit 4 -- -- BCR4 BCR12 MBCR4 MBCR12 TXPR4 TXPR12 TXCR4 TXCR12 TXACK4 TXACK12 ABACK4 ABACK12 RXPR4 RXPR12 RFPR4 RFPR12 IRR4 IRR12 MBIMR4 MBIMR12 IMR4 IMR12 Bit 4 Bit 4 UMSR4 UMSR12 LAFML4 LAFML12 -- LAFMH12 -- -- -- -- Bit 3 -- GSR3 BCR3 BCR11 MBCR3 MBCR11 TXPR3 TXPR11 TXCR3 TXCR11 TXACK3 TXACK11 ABACK3 ABACK11 RXPR3 RXPR11 RFPR3 RFPR11 IRR3 -- MBIMR3 MBIMR11 IMR3 -- Bit 3 Bit 3 UMSR3 UMSR11 LAFML3 LAFML11 -- LAFMH11 DLC3 -- -- -- Bit 2 MCR2 GSR2 BCR2 BCR10 MBCR2 MBCR10 TXPR2 TXPR10 TXCR2 TXCR10 TXACK2 TXACK10 ABACK2 ABACK10 RXPR2 RXPR10 RFPR2 RFPR10 IRR2 -- MBIMR2 MBIMR10 IMR2 -- Bit 2 Bit 2 UMSR2 UMSR10 LAFML2 LAFML10 -- LAFMH10 DLC2 -- -- -- Bit 1 MCR1 GSR1 BCR1 BCR9 MBCR1 MBCR9 TXPR1 TXPR9 TXCR1 TXCR9 TXACK1 TXACK9 ABACK1 ABACK9 RXPR1 RXPR9 RFPR1 RFPR9 IRR1 IRR9 MBIMR1 MBIMR9 IMR1 IMR9 Bit 1 Bit 1 UMSR1 UMSR9 LAFML1 LAFML9 LAFMH1 LAFMH9 DLC1 -- -- -- Bit 0 MCR0 GSR0 BCR0 BCR8 -- MBCR8 -- TXPR8 -- TXCR8 -- TXACK8 -- ABACK8 RXPR0 RXPR8 RFPR0 RFPR8 IRR0 IRR8 MBIMR0 MBIMR8 -- IMR8 Bit 0 Bit 0 UMSR0 UMSR8 LAFML0 LAFML8 LAFMH0 LAFMH8 DLC0 -- -- -- Module HCAN
Rev. 0.5, 03/03, page 395 of 438
Register Name MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6]
Bit 7 ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28
Bit 6 ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27
Bit 5 ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26
Bit 4 RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25
Bit 3 IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24
Bit 2 -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23
Bit 1 ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22
Bit 0 ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21
Module HCAN
Rev. 0.5, 03/03, page 396 of 438
Register Name MC5[7] MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] MC8[7] MC8[8] MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7] MC9[8] MC10[1] MC10[2] MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8]
Bit 7 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15
Bit 6 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14
Bit 5 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13
Bit 4 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12
Bit 3 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11
Bit 2 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10
Bit 1 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9
Bit 0 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8
Module HCAN
Rev. 0.5, 03/03, page 397 of 438
Register Name MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] MC14[1] MC14[2] MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD0[1] MD0[2]
Bit 7 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 -- -- -- -- ID-20 ID-28 ID-7 ID-15 Bit 7 Bit 7
Bit 6 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 -- -- -- -- ID-19 ID-27 ID-6 ID-14 Bit 6 Bit 6
Bit 5 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 -- -- -- -- ID-18 ID-26 ID-5 ID-13 Bit 5 Bit 5
Bit 4 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 -- -- -- -- RTR ID-25 ID-4 ID-12 Bit 4 Bit 4
Bit 3 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 DLC3 -- -- -- IDE ID-24 ID-3 ID-11 Bit 3 Bit 3
Bit 2 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 DLC2 -- -- -- -- ID-23 ID-2 ID-10 Bit 2 Bit 2
Bit 1 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 DLC1 -- -- -- ID-17 ID-22 ID-1 ID-9 Bit 1 Bit 1
Bit 0 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 DLC0 -- -- -- ID-16 ID-21 ID-0 ID-8 Bit 0 Bit 0
Module HCAN
Rev. 0.5, 03/03, page 398 of 438
Register Name MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] MD4[1] MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4]
Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7
Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6
Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5
Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4
Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Module HCAN
Rev. 0.5, 03/03, page 399 of 438
Register Name MD5[5] MD5[6] MD5[7] MD5[8] MD6[1] MD6[2] MD6[3] MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6] MD7[7] MD7[8] MD8[1] MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] MD10[6]
Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7
Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6
Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5
Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4
Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Module HCAN
Rev. 0.5, 03/03, page 400 of 438
Register Name MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4] MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] MD14[7] MD14[8] MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8]
Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7
Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6
Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5
Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4
Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Module HCAN
Rev. 0.5, 03/03, page 401 of 438
Register Name HCANMON SBYCR SYSCR SCKCR MDCR MSTPCRA MSTPCRB MSTPCRC LPWRCR ISCRH ISCRL IER ISR P1DDR PADDR PBDDR PCDDR PDDDR PFDDR PAPCR PBPCR PCPCR PDPCR PAODR PBODR PCODR TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3
Bit 7 RxDIE SSBY MACS PSTOP -- MSTPA7 MSTPB7 MSTPC7 DTON -- IRQ3SCB -- -- P17DDR -- PB7DDR PC7DDR PD7DDR PF7DDR -- PB7PCR PC7PCR PD7PCR -- PB7ODR PC7ODR CCLR2 -- IOB3 IOD3 TTGE -- Bit15 Bit7
Bit 6 TxSTP STS2 -- -- -- MSTPA6 MSTPB6 MSTPC6 LSON -- IRQ3SCA -- -- P16DDR -- PB6DDR PC6DDR PD6DDR PF6DDR -- PB6PCR PC6PCR PD6PCR -- PB6ODR PC6ODR CCLR1 -- IOB2 IOD2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6
Bit 5 -- STS1 INTM1 -- -- MSTPA5 MSTPB5 MSTPC5 -- -- IRQ2SCB IRQ5E IRQ5F P15DDR -- PB5DDR PC5DDR PD5DDR PF5DDR -- PB5PCR PC5PCR PD5PCR -- PB5ODR PC5ODR CCLR0 BFB IOB1 IOD1 -- -- Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5
Bit 4 -- STS0 INTM0 -- -- MSTPA4 MSTPB4 MSTPC4 SUBSTP -- IRQ2SCA IRQ4E IRQ4F P14DDR -- PB4DDR PC4DDR PD4DDR PF4DDR -- PB4PCR PC4PCR PD4PCR -- PB4ODR PC4ODR CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4
Bit 3 -- -- NMIEG STCS -- MSTPA3 MSTPB3 MSTPC3 RFCUT IRQ5SCB IRQ1SCB IRQ3E IRQ3F P13DDR PA3DDR PB3DDR PC3DDR -- PF3DDR PA3PCR PB3PCR PC3PCR -- PA3ODR PB3ODR PC3ODR CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3
Bit 2 -- -- -- SCK2 MDS2 MSTPA2 MSTPB2 MSTPC2 -- IRQ5SCA IRQ1SCA IRQ2E IRQ2F P12DDR PA2DDR PB2DDR PC2DDR -- PF2DDR PA2PCR PB2PCR PC2PCR -- PA2ODR PB2ODR PC2ODR TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2
Bit 1 TxD -- -- SCK1 MDS1 MSTPA1 MSTPB1 MSTPC1 STC1 IRQ4SCB IRQ0SCB IRQ1E IRQ1F P11DDR PA1DDR PB1DDR PC1DDR -- PF1DDR PA1PCR PB1PCR PC1PCR -- PA1ODR PB1ODR PC1ODR TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1
Bit 0 RxD -- RAME SCK0 MDS0 MSTPA0 MSTPB0 MSTPC0 STC0 IRQ4SCA IRQ0SCA IRQ0E IRQ0F P10DDR PA0DDR PB0DDR PC0DDR -- PF0DDR PA0PCR PB0PCR PC0PCR -- PA0ODR PB0ODR PC0ODR TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0
Module HCAN System
INT
PORT
TPU_3
TGRA_3
Bit15 Bit7
TGRB_3
Bit15 Bit7
TGRC_3
Bit15 Bit7
TGRD_3
Bit15 Bit7
Rev. 0.5, 03/03, page 402 of 438
Register Name TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4
Bit 7 -- -- IOB3 TTGE TCFD Bit15 Bit7
Bit 6 CCLR1 -- IOB2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 -- IOB2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 -- -- IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 -- P16DR -- PB6DR PC6DR PD6DR PF6DR
Bit 5 CCLR0 -- IOB1 TCIEU TCFU Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 -- IOB1 TCIEU TCFU Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CST5 SYNC5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 -- P15DR -- PB5DR PC5DR PD5DR PF5DR
Bit 4 CKEG1 -- IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 -- IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CST4 SYNC4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 -- P14DR -- PB4DR PC4DR PD4DR PF4DR
Bit 3 CKEG0 MD3 IOA3 -- -- Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 -- -- Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CST3 SYNC3 -- -- -- -- -- -- -- -- -- -- RAMS P13DR PA3DR PB3DR PC3DR -- PF3DR
Bit 2 TPSC2 MD2 IOA2 -- -- Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 -- -- Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 CST2 SYNC2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 RAM2 P12DR PA2DR PB2DR PC2DR -- PF2DR
Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 CST1 SYNC1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 RAM1 P11DR PA1DR PB1DR PC1DR -- PF1DR
Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 CST0 SYNC0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 RAM0 P10DR PA0DR PB0DR PC0DR -- PF0DR
Module TPU_4
TGRA_4
Bit15 Bit7
TGRB_4
Bit15 Bit7
TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5
-- -- IOB3 TTGE TCFD Bit15 Bit7
TPU_5
TGRA_5
Bit15 Bit7
TGRB_5
Bit15 Bit7
TSTR TSYR IPRA IPRB IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRM RAMER P1DR PADR PBDR PCDR PDDR PFDR
-- -- -- -- -- -- -- -- -- -- -- -- -- P17DR -- PB7DR PC7DR PD7DR PF7DR
TPU common
INT
ROM PORT
Rev. 0.5, 03/03, page 403 of 438
Register Name TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0
Bit 7 CCLR2 -- IOB3 IOD3 TTGE -- Bit15 Bit7
Bit 6 CCLR1 -- IOB2 IOD2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 -- IOB2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 -- IOB2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 WT/IT Bit6 RSTE
Bit 5 CCLR0 BFB IOB1 IOD1 -- -- Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 -- IOB1 TCIEU TCFU Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 -- IOB1 TCIEU TCFU Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 TME Bit5 RSTS
Bit 4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 -- IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 -- IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 -- Bit4 --
Bit 3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 -- -- Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 -- -- Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 -- Bit3 --
Bit 2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 -- -- Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 -- -- Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 CKS2 Bit2 --
Bit 1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 CKS1 Bit1 --
Bit 0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 CKS0 Bit0 --
Module TPU_0
TGRA_0
Bit15 Bit7
TGRB_0
Bit15 Bit7
TGRC_0
Bit15 Bit7
TGRD_0
Bit15 Bit7
TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1
-- -- IOB3 TTGE TCFD Bit15 Bit7
TPU_1
TGRA_1
Bit15 Bit7
TGRB_1
Bit15 Bit7
TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2
-- -- IOB3 TTGE TCFD Bit15 Bit7
TPU_2
TGRA_2
Bit15 Bit7
TGRB_2
Bit15 Bit7
TCSR_0 TCNT_0 RSTCSR
OVF Bit7 WOVF
WDT_0
Rev. 0.5, 03/03, page 404 of 438
Register Name SMR_0*3 (SMR_0*4) BRR_0 SCR_0 TDR_0 SSR_0*3 (SSR_0*4) RDR_0 SCMR_0 SMR_1*3 (SMR_1*4) BRR_1 SCR_1 TDR_1 SSR_1*3 (SSR_1*4) RDR_1 SCMR_1 SMR_2*3 (SMR_2*4) BRR_2 SCR_2 TDR_2 SSR_2*3 (SSR_2*4) RDR_2 SCMR_2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 FLMCR1 FLMCR2 EBR1 FLPWCR
Bit 7 C/A (GM) Bit7 TIE Bit7 TDRE (TDRE) Bit7 -- C/A (GM) Bit7 TIE Bit7 TDRE (TDRE) Bit7 -- C/A (GM) Bit7 TIE Bit7 TDRE (TDRE) Bit7 -- AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGS1 OVF Bit7 FWE FLER EB7 PDWND
Bit 6 CHR (BLK) Bit6 RIE Bit6 RDRF (RDRF) Bit6 -- CHR (BLK) Bit6 RIE Bit6 RDRF (RDRF) Bit6 -- CHR (BLK) Bit6 RIE Bit6 RDRF (RDRF) Bit6 -- AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT Bit6 SWE -- EB6 --
Bit 5 PE (PE) Bit5 TE Bit5 ORER (ORER) Bit5 -- PE (PE) Bit5 TE Bit5 ORER (ORER) Bit5 -- PE (PE) Bit5 TE Bit5 ORER (ORER) Bit5 -- AD7 -- AD7 -- AD7 -- AD7 -- ADST -- TME Bit5 ESU1 -- EB5 --
Bit 4 O/E (O/E) Bit4 RE Bit4 FER (ERS) Bit4 -- O/E (O/E) Bit4 RE Bit4 FER (ERS) Bit4 -- O/E (O/E) Bit4 RE Bit4 FER (ERS) Bit4 -- AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- PSS Bit4 PSU1 -- EB4 --
Bit 3 STOP (BCP1) Bit3 MPIE Bit3 PER (PER) Bit3 SDIR STOP (BCP1) Bit3 MPIE Bit3 PER (PER) Bit3 SDIR STOP (BCP1) Bit3 MPIE Bit3 PER (PER) Bit3 SDIR AD5 -- AD5 -- AD5 -- AD5 -- CH3 CKS1 RST/NMI Bit3 EV1 -- EB3 --
Bit 2 MP (BCP0) Bit2 TEIE Bit2 TEND (TEND) Bit2 SINV MP (BCP0) Bit2 TEIE Bit2 TEND (TEND) Bit2 SINV MP (BCP0) Bit2 TEIE Bit2 TEND (TEND) Bit2 SINV AD4 -- AD4 -- AD4 -- AD4 -- CH2 CKS0 CKS2 Bit2 PV1 -- EB2 --
Bit 1 CKS1 (CKS1) Bit1 CKE1 Bit1 MPB (MPB) Bit1 -- CKS1 (CKS1) Bit1 CKE1 Bit1 MPB (MPB) Bit1 -- CKS1 (CKS1) Bit1 CKE1 Bit1 MPB (MPB) Bit1 -- AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- CKS1 Bit1 E1 -- EB1 --
Bit 0 CKS0 (CKS0) Bit0 CKE0 Bit0 MPBT (MPBT) Bit0 SMIF CKS0 (CKS0) Bit0 CKE0 Bit0 MPBT (MPBT) Bit0 SMIF CKS0 (CKS0) Bit0 CKE0 Bit0 MPBT (MPBT) Bit0 SMIF AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- CKS0 Bit0 P1 -- EB0 --
Module SCI_0
SCI_1
SCI_2
A/D
WDT_1
ROM
Rev. 0.5, 03/03, page 405 of 438
Register Name PORT1 PORT4 PORT9 PORTA PORTB PORTC PORTD PORTF
Bit 7 P17 P47 P97 -- PB7 PC7 PD7 PF7
Bit 6 P16 P46 P96 -- PB6 PC6 PD6 PF6
Bit 5 P15 P45 P95 -- PB5 PC5 PD5 PF5
Bit 4 P14 P44 P94 -- PB4 PC4 PD4 PF4
Bit 3 P13 P43 P93 PA3 PB3 PC3 -- PF3
Bit 2 P12 P42 P92 PA2 PB2 PC2 -- PF2
Bit 1 P11 P41 P91 PA1 PB1 PC1 -- PF1
Bit 0 P10 P40 P90 PA0 PB0 PC0 -- PF0
Module PORT
Notes: 1. 2. 3. 4.
For buffer operation. For free operation. Normal serial communication interface mode. Smart Card interface mode. Some bit functions of SMR differ in normal serial communication interface mode and Smart Card interface mode.
Rev. 0.5, 03/03, page 406 of 438
17.3
Register States in Each Operating Mode
Reset Highspeed Mediumspeed Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Module Stop Watch Software Hardware Subactive Subsleep Standby Standby Module
Register Name MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] MC3[3] MC3[4] MC3[5]
Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized -
Initialized Initialized Initialized Initialized Initialized Initialized HCAN Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 0.5, 03/03, page 407 of 438
Register Name MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6] MC5[7] MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] MC8[7] MC8[8] MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7]
Reset
Highspeed
Mediumspeed Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Module Stop
Watch
Software Hardware Subactive Subsleep Standby Standby Module
Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized -
Initialized Initialized Initialized Initialized Initialized Initialized HCAN Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 0.5, 03/03, page 408 of 438
Register Name MC9[8] MC10[1] MC10[2] MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] MC14[1] MC14[2] MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD0[1]
Reset
Highspeed
Mediumspeed Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Module Stop
Watch
Software Hardware Subactive Subsleep Standby Standby Module
Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized -
Initialized Initialized Initialized Initialized Initialized Initialized HCAN Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 0.5, 03/03, page 409 of 438
Register Name MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] MD4[1] MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6] MD5[7] MD5[8] MD6[1] MD6[2] MD6[3]
Reset
Highspeed
Mediumspeed Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Module Stop
Watch
Software Hardware Subactive Subsleep Standby Standby Module
Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized -
Initialized Initialized Initialized Initialized Initialized Initialized HCAN Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 0.5, 03/03, page 410 of 438
Register Name MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6] MD7[7] MD7[8] MD8[1] MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4] MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5]
Reset
Highspeed
Mediumspeed Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Module Stop
Watch
Software Hardware Subactive Subsleep Standby Standby Module
Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized -
Initialized Initialized Initialized Initialized Initialized Initialized HCAN Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 0.5, 03/03, page 411 of 438
Register Name MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] MD14[7] MD14[8] MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] HCANMON SBYCR SYSCR SCKCR MDCR MSTPCRA MSTPCRB MSTPCRC LPWRCR ISCRH ISCRL IER ISR P1DDR PADDR PBDDR PCDDR PDDDR PFDDR PAPCR PBPCR PCPCR PDPCR
Reset
Highspeed
Mediumspeed Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Module Stop
Watch
Software Hardware Subactive Subsleep Standby Standby Module
Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized -
Initialized Initialized Initialized Initialized Initialized Initialized HCAN Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Initialized SYSTEM Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized INT Initialized Initialized Initialized Initialized PORT Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 0.5, 03/03, page 412 of 438
Register Name PAODR PBODR PCODR TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 TSTR TSYR IPRA IPRB IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRM RAMER P1DR PADR PBDR PCDR PDDR PFDR
Reset
Highspeed
Mediumspeed Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Module Stop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Watch - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Software Hardware Subactive Subsleep Standby Standby Module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Initialized PORT Initialized Initialized Initialized TPU_3 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_4 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_5 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU common Initialized Initialized INT Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized ROM Initialized PORT Initialized Initialized Initialized Initialized Initialized
Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized -
Rev. 0.5, 03/03, page 413 of 438
Register Name TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCSR_0 TCNT_0 RSTCSR SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2
Reset
Highspeed
Mediumspeed Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Module Stop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Watch - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Software Hardware Subactive Subsleep Standby Standby Module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Initialized TPU_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT_0 Initialized Initialized
Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized -
Initialized Initialized Initialized Initialized Initialized Initialized SCI_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 0.5, 03/03, page 414 of 438
Register Name SCMR_2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 FLMCR1 FLMCR2 EBR1 FLPWCR PORT1 PORT4 PORT9 PORTA PORTB PORTC PORTD PORTF
Reset
Highspeed
Mediumspeed Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - - - - - -
Watch
Software Hardware Subactive Subsleep Standby Standby Module
Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized -
Initialized Initialized Initialized Initialized Initialized SCI_2 Initialized Initialized Initialized Initialized Initialized A/D Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Initialized WDT_1 Initialized Initialized ROM Initialized Initialized Initialized Initialized PORT Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Note: - is not initialized.
Rev. 0.5, 03/03, page 415 of 438
Rev. 0.5, 03/03, page 416 of 438
Section 18 Electrical Characteristics
18.1 Absolute Maximum Ratings
Table 18.1 lists the absolute maximum ratings. Table 18.1 Absolute Maximum Ratings
Item Power supply voltage Input voltage (XTAL, EXTAL) Input voltage (port 4 and 9) Input voltage (except XTAL, EXTAL, port 4 and 9) Analog power supply voltage Analog input voltage Operating temperature Symbol VCC Vin Vin Vin AVCC VAN Topr Tstg Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to VCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature -55 to +125 Unit V V V V V V C C C
Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.
Rev. 0.5, 03/03, page 417 of 438
18.2
DC Characteristics
Table 18.2 lists the DC characteristics. Table 18.3 lists the permissible output currents. Table 18.2 DC Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range 1 specifications)*
Item Symbol
-
Min. VCC x 0.2 --
Typ. -- -- -- --
Max. -- VCC x 0.7 -- VCC + 0.3
Unit V V V V
Test Conditions
Schmitt trigger IRQ0 to IRQ5 VT + input voltage VT VT - VT Input high voltage RES, STBY, NMI, MD2 to MD0, FWE EXTAL Port 1, A to D, F, HRxD Port 4 and 9 Input low voltage RES, STBY, NMI, MD2 to MD0, FWE EXTAL Port 1, A to D, F, HRxD Port 4, 9 Output high voltage Output low voltage All output pins VOH All output pins VOL | Iin | VIL VIH
+ -
VCC x 0.05 VCC x 0.9
VCC x 0.7 VCC x 0.7 AVCC x 0.7 -0.3
-- -- -- --
VCC + 0.3 VCC + 0.3
V V
AVCC + 0.3 V VCC x 0.1 V
-0.3 -0.3 -0.3 VCC - 0.5 VCC - 1.0 -- -- --
-- -- -- -- -- -- -- --
VCC x 0.2 VCC x 0.2
V V
AVCC x 0.2 V -- -- 0.4 1.0 1.0 V V V A A IOH = -200 A IOH = -1 mA IOL = 1.6 mA Vin = 0.5 to VCC - 0.5 V
Input leakage RES current STBY, NMI, MD2 to MD0, FWE, HRxD Port 4, 9
--
--
1.0
A
Vin = 0.5 to AVCC - 0.5 V
Rev. 0.5, 03/03, page 418 of 438
Item MOS input Port A to D pull-up current Input capacitance RES NMI All input pins except RES and NMI Current Normal 2 consumption* operation Sleep mode All modules stopped
Symbol -IP Cin
Min. 30 -- -- --
Typ. -- -- -- --
Max. 300 30 30 15
Unit A pF pF pF
Test Conditions Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C
ICC*
3
-- -- --
TBD mA TBD VCC = 5.0 V VCC = 5.5 V TBD TBD mA VCC = 5.0 V VCC = 5.5 V TBD -- mA
f = 20 MHz f = 20 MHz f = 20 MHz, VCC = 5.0 V (reference values) f = 20 MHz, VCC = 5.0 V (reference values) Ta 50C 50C < Ta AVCC = 5.0 V
Mediumspeed mode (/32) Standby mode Analog During A/D power supply conversion current Idle VRAM AlCC
--
TBD
--
mA
-- -- -- -- 2.0
TBD -- 2.5 -- --
TBD TBD 4.0 5.0 --
A A mA A V
RAM standby voltage
Notes: 1. If the A/D converter is not used, do not leave the AVCC, and AVSS pins open. Apply a voltage between 4.0 V and 5.5 V to the AVCC pin by connecting them to VCC, for instance. 2. Current consumption values are for VIH = VCC (EXTAL), AVCC (ports 4 and 9), or VCC (other), and VIL = 0 V, with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. 3. ICC depends on VCC and f as follows: ICC (max.) = TBD (normal operation) ICC (max.) = TBD (sleep mode)
Rev. 0.5, 03/03, page 419 of 438
Table 18.3 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*
Item Permissible output low current (per pin) Permissible output low current (total) All output pins Total of all output pins VCC = 4.5 to 5.5 V VCC = 4.5 to 5.5 V VCC = 4.5 to 5.5 V VCC = 4.5 to 5.5 V Symbol Min. IOL IOL -IOH -IOH -- -- -- -- Typ. -- -- -- -- Max. 10 100 2.0 30 Unit mA mA mA mA
Permissible output All output high current (per pin) pins Permissible output high current (total) Note: * Total of all output pins
To protect chip reliability, do not exceed the output current values in table 18.3.
18.3
AC Characteristics
Figure 18.1 shows the test conditions for the AC characteristics.
5V C=30pF: All ports RL= 2.4k RH=12 Input/output timing measurement levels * Low level : 0.8V * High level : 2.0V
RL LSI output pin C RH
Figure 18.1 Output Load Circuit
Rev. 0.5, 03/03, page 420 of 438
18.3.1
Clock Timing
Table 18.4 lists the clock timing Table 18.4 Clock Timing Conditions : VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, = 4 MHz to 24 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications)
Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Oscillation stabilization time at reset (crystal) Oscillation stabilization time in software standby (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT Min. 41.6 TBD TBD -- -- 20 8 2 Max. 250 -- -- TBD TBD -- -- -- Unit ns ns ns ns ns ms ms ms Figure 18.3 Figure 18.3 Figure 18.3 Test Conditions Figure 18.2
tcyc tCH tCf
tCL
tCr
Figure 18.2 System Clock Timing
Rev. 0.5, 03/03, page 421 of 438
EXTAL tDEXT VCC tDEXT
tOSC1
tOSC1
Figure 18.3 Oscillation Stabilization Timing 18.3.2 Control Signal Timing
Table 18.5 lists the control signal timing. Table 18.5 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, = 4 MHz to 24 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications)
Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- Unit ns tcyc ns ns ns ns ns ns Figure 18.5 Test Conditions Figure 18.4
Rev. 0.5, 03/03, page 422 of 438
tRESS
tRESS
tRESW
Figure 18.4 Reset Input Timing
tNMIS NMI tNMIW tNMIH
(i = 0 to 5) tIRQS
tIRQW tIRQH
Edge input tIRQS
Level input
Figure 18.5 Interrupt Input Timing
Rev. 0.5, 03/03, page 423 of 438
18.3.3
Timing of On-Chip Peripheral Modules
Table 18.6 lists the timing of on-chip peripheral modules. Table 18.6 Timing of On-Chip Peripheral Modules Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, = 4 MHz to 24 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications)
Item I/O port Output data delay time Symbol tPWD Min. -- 25 25 -- 25 25 1.5 2.5 4 6 tSCKW tSCKr tSCKf tTXD tRXS tRXH 0.4 -- -- -- 40 40 Max. 40 -- -- 40 -- -- -- -- -- -- 0.6 1.5 1.5 40 -- -- ns Figure 18.10 tScyc tcyc tcyc Figure 18.9 ns tcyc Figure 18.8 ns Figure 18.7 Unit ns Test Conditions Figure 18.6
Input data setup time tPRS Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width SCI Input clock cycle Single edge Both edges tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL
Asynchro- tScyc nous Synchronous
Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous)
Rev. 0.5, 03/03, page 424 of 438
Item A/D Trigger input setup converter time HCAN* Transmit data delay time Transmit data setup time Transmit data hold time Note: *
Symbol tTRGS tHTXD tHRXS tHRXH
Min. 30 -- 80 80
Max. -- 80 -- --
Unit ns ns
Test Conditions Figure 18.11 Figure 18.12
The HCAN input signal is asynchronous. However, its state is judged to have changed at the rising-edge (two clock cycles) of the CK clock signal shown in figure 18.12. The HCAN output signal is also asynchronous. Its state changes based on the rising-edge (two clock cycles) of the CK clock signal shown in figure 18.12.
T1
T2
tPRS Port 1, 4, 9 A to D, F (read) tPWD Port 1, A to D, F (write) tPRH
Figure 18.6 I/O Port Input/Output Timing
tTOCD Output compare output*
tTICS Input capture input*
Note : * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Figure 18.7 TPU Input/Output Timing
Rev. 0.5, 03/03, page 425 of 438
tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS
Figure 18.8 TPU Clock Input Timing
tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf
Figure 18.9 SCK Clock Input Timing
SCK0 to SCK2
tTXD TxD0 to TxD2 (transmit data) tRXS RxD0 to RxD2 (receive data) tRXH
Figure 18.10 SCI Input/Output Timing (Clocked Synchronous Mode)
tTRGS
Figure 18.11 A/D Converter External Trigger Input Timing
Rev. 0.5, 03/03, page 426 of 438
VOL
VOL
tHTXD HTxD (transmit data) tHRXS HRxD (receive data) tHRXH
Figure 18.12 HCAN Input/Output Timing
18.4
A/D Conversion Characteristics
Table 18.7 lists the A/D conversion characteristics. Table 18.7 A/D Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0V, = 4 MHz to 24 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications)
Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Min. 10 10 -- -- -- -- -- -- -- Typ. 10 -- -- -- -- -- -- 0.5 -- Max. 10 200 20 5 3.5 3.5 3.5 -- 4.0 Unit bits s pF k LSB LSB LSB LSB LSB
Rev. 0.5, 03/03, page 427 of 438
18.5
Flash Memory Characteristics
Table 18.8 lists the flash memory characteristics. Table 18.8 Flash Memory Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = 0 to +75C (Programming/erasing operating temperature range)
Item Programming time*1, *2, *4 Erase time* * *
1, 3, 5
Symbol tP tE NWEC
1
Min. Typ. Max. Unit -- -- -- 1 50 28 198 8 10 100 -- 1 50 30 200 10 200 100 -- -- 32 202 12 ms/128 bytes Times s s s s s
Test Condition
1200 ms/block
Reprogramming count Programming Wait time after SWE bit setting* Wait time after PSU1 bit setting*1 Wait time after P1 bit setting*1, *4
tsswe tspsu tsp30 tsp200 tsp10
Programming time wait Programming time wait Additionalprogramming time wait
Wait time after P1 bit clear*1 Wait time after PSU1 bit clear*
1
tcp tcpsu tspv
1
5 5 4 2 2 100 -- 1 100 10 10 10 20 2 4 100 12
5 5 4 2 2 100 -- 1 100 10 10 10 20 2 4 100 --
-- -- -- -- -- -- -- -- 100 -- -- -- -- -- -- 120
s s s s s s s s ms s s s s s s Times Erase time wait
Wait time after PV1 bit setting*1 Wait time after PV1 bit clear*1 Wait time after SWE bit clear*1 Maximum programming count*1, *4 Erase Wait time after SWE bit setting*1 Wait time after ESU1 bit setting*1 Wait time after E1 bit setting*1, *5 Wait time after E1 bit clear*1 Wait time after ESU1 bit clear*1 Wait time after EV1 bit setting*1
1
Wait time after H'FF dummy write* tspvr tcpv tcswe N tsswe tsesu tse tce tcesu tsev tcev
1
1000 Times
Wait time after H'FF dummy write* tsevr Wait time after EV1 bit clear*1 Wait time after SWE bit clear* Maximum erase count*1, *5 tcswe N
Rev. 0.5, 03/03, page 428 of 438
Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P1 bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E1 bit in FLMCR1 is set. It does not include the erase verification time.) 4. To specify the maximum programming time value (tp (max.)) in the 128-bytes programming algorithm, set the max. value (1000) for the maximum programming count (N). The wait time after P1 bit setting should be changed as follows according to the value of the programming counter(n). Programming counter(n) = 1 to 6: tsp30 = 30 s Programming counter(n) = 7 to 1000: tsp200 = 200 s [In additional programming] Programming counter(n) = 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE(max.)), the following relationship applies between the wait time after E1 bit setting (tse) and the maximum erase count (N): tE (max.) = Wait time after E1 bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy the above formula. Examples: When tse = 100 ms, N = 12 times When tse = 10 ms, N = 120 times
Rev. 0.5, 03/03, page 429 of 438
Rev. 0.5, 03/03, page 430 of 438
Appendix
A. I/O Port States in Each Pin State
MCU Operating Mode 7 7 7 7 7 7 7 7 Hardware Standby Mode T T T T T T T T Software Standby Mode Keep T T Keep Keep Keep Keep [DDR = 0] T [DDR = 1] H PF6 PF5 PF4 PF3 PF2 PF1 PF0 HTxD HRxD 7 7 H Input T T H T Output Input 7 T T Keep Program Execution State Sleep Mode I/O port Input port Input port I/O port I/O port I/O port I/O port [DDR = 0] T [DDR = 1] Clock output I/O port
Port Name Port 1 Port 4 Port 9 Port A Port B Port C Port D PF7
Reset T T T T T T T T
Legend H: High level T: High impedance Keep: Input port becomes high-impedance, output port retains state
Rev. 0.5, 03/03, page 431 of 438
B.
Product Code Lineup
Product Classification Type Name HD64F2615 HD6432615 Model Marking HD64F2615 HD6432615 Package (Code) 80-pin QFP (FP-80Q) Flash memory version Masked ROM version* In planning
H8S/2615 Note: *
Rev. 0.5, 03/03, page 432 of 438
C.
Package Dimensions
The package dimension that is shown in the Hitachi Semiconductor Package Data Book has priority.
17.2 0.2
14
Unit: mm
41 40
60 61
17.2 0.2
80 1
*0.32 0.08 0.30 0.06
21 20
0.65
0.12 M 0.83
3.05 Max
*0.17 0.05 0.15 0.04
2.70
1.6
0.10 +0.15 -0.10
0 - 8
0.8 0.2
Hitachi Code JEDEC JEITA Mass (reference value) FP-80Q -- Conforms 1.2 g
0.10
*Dimension including the plating thickness
Base material dimension
Figure C.1 FP-80Q Package Dimensions
Rev. 0.5, 03/03, page 433 of 438
Rev. 0.5, 03/03, page 434 of 438
Index
16-Bit Timer Pulse Unit (TPU) .............. 113 Buffer Operation ................................. 157 Cascaded Operation ............................ 161 Free-running count operation.............. 151 Phase Counting Mode......................... 167 PWM Modes....................................... 162 Synchronous Operation....................... 156 Toggle output...................................... 152 Waveform Output by Compare Match 152 A/D Converter ........................................ 311 A/D Converter Activation................... 175 A/D trigger input................................. 110 Conversion Time................................. 319 External Trigger .................................. 321 Scan Mode .......................................... 318 Single Mode........................................ 318 Address Map ............................................. 49 Address Space........................................... 16 Addressing Modes .................................... 37 Absolute Address.................................. 38 Immediate ............................................. 39 Memory Indirect ................................... 39 Program-Counter Relative .................... 39 Register Direct ...................................... 37 Register Indirect.................................... 37 Register Indirect with Displacement..... 37 Register Indirect with Post-Increment .. 38 Register Indirect with Pre-Decrement... 38 Bcc ...................................................... 25, 33 Bit Rate ................................................... 296 Bus cycle................................................... 81 Clock Pulse Generator ............................ 351 Condition Field ......................................... 36 Condition-Code Register (CCR)............... 20 CPU Operating Modes.............................. 12 Advanced Mode.................................... 13 Normal Mode ........................................12 Data direction register ...............................85 Data register ..............................................85 Effective Address ......................................40 Effective Address Extension .....................36 Exception Handling...................................51 Interrupts ...............................................56 Reset Exception Handling.....................53 Stack Status ...........................................58 Traces....................................................56 Trap Instruction.....................................57 Exception Handling Vector Table.............52 Extended Control Register (EXR).............19 General Registers ......................................18 Hitachi Controller Area Network (HCAN)...................................................265 11 consecutive recessive bits...............293 Arbitration field...........................300, 303 Buffer segment ....................................296 Configuration mode ............................293 Control field ........................................300 Data field.............................................300 Data frame...........................................303 HCAN Halt Mode ...............................306 HCAN Sleep Mode .............................305 Mailbox .......................................289, 291 Message Control (MC0 to MC15) ......289 Message Data (MD0 to MD15)...........291 Message transmission cancellation .....300 Message Transmission Method ...........298 Remote frame ......................................304 Remote transmission request bit .........304 Unread message overwrite ..................304 Input pull-up MOS ....................................85
Rev. 0.5, 03/03, page 435 of 438
Instruction Set........................................... 25 Arithmetic Operations Instructions....... 28 Bit Manipulation Instructions ............... 31 Block Data Transfer Instructions .......... 35 Branch Instructions ............................... 33 Data Transfer Instructions .................... 27 Logic Operations Instructions............... 30 Shift Instructions................................... 30 System Control Instructions.................. 34 Interrupt Control Modes ........................... 72 Interrupt Controller ................................... 61 Interrupt Exception Handling Vector Table .................................................................. 69 Interrupt Mask Bit..................................... 20 Interrupt mask level .................................. 19 Interrupt priority register (IPR)................. 61 Interrupts ADI ..................................................... 321 ERS0/OVR0 ....................................... 307 NMI ................................................ 68, 79 RM0 .................................................... 307 RM1 .................................................... 307 SLE0 ................................................... 307 TCI0V................................................. 174 TCI1U................................................. 174 TCI1V................................................. 174 TCI2U................................................. 174 TCI2V................................................. 174 TCI3V................................................. 174 TCI4U................................................. 174 TCI4V................................................. 174 TCI5U................................................. 174 TCI5V................................................. 174 TGI0A................................................. 174 TGI0B................................................. 174 TGI0C................................................. 174 TGI0D................................................. 174 TGI1A................................................. 174 TGI1B................................................. 174 TGI2A................................................. 174 TGI2B................................................. 174 TGI3A................................................. 174
Rev. 0.5, 03/03, page 436 of 438
TGI3B ................................................. 174 TGI3C ................................................. 174 TGI3D................................................. 174 TGI4A................................................. 174 TGI4B ................................................. 174 TGI5A................................................. 174 TGI5B ................................................. 174 WOVI.................................................. 200 MAC instruction ....................................... 46 Memory cycle ........................................... 81 Multiply-Accumulate Register (MAC) ..... 21 On-Board Programming.......................... 339 Open-drain control register ....................... 85 Operating Mode Selection......................... 45 Operation Field ......................................... 36 PLL Circuit ............................................. 357 Port register............................................... 85 Power-Down Modes Direct Transitions................................ 378 Subactive Mode .................................. 378 Subsleep Mode.................................... 377 Watch Mode........................................ 376 Program Counter (PC) .............................. 19 Program/Erase Protection ....................... 349 Programmer Mode .................................. 350 Register Field ............................................ 36 Registers ABACK....................... 277, 382, 395, 407 ADCR ......................... 317, 394, 405, 415 ADCSR ....................... 315, 394, 405, 415 ADDR ......................... 314, 394, 405, 415 BCR ............................ 271, 382, 395, 407 BRR ............................ 218, 393, 405, 414 EBR1........................... 337, 394, 405, 415 FLMCR1 ..................... 336, 394, 405, 415 FLMCR2 ..................... 337, 394, 405, 415 FLPWCR..................... 339, 394, 405, 415 GSR............................. 269, 382, 395, 407
HCANMON................ 291, 390, 402, 412 IER................................ 65, 390, 402, 412 IMR............................. 284, 382, 395, 407 IPR ................................ 64, 392, 403, 413 IRR.............................. 280, 382, 395, 407 ISCR ............................. 66, 390, 402, 412 ISR ................................ 68, 390, 402, 412 LAFMH ...................... 287, 382, 395, 407 LAFML....................... 287, 382, 395, 407 LPWRCR.................... 367, 390, 402, 412 MBCR......................... 273, 382, 395, 407 MBIMR....................... 283, 382, 395, 407 MC .............................. 289, 382, 395, 407 MCR ........................... 268, 382, 395, 407 MD.............................. 291, 386, 398, 409 MDCR........................... 46, 390, 402, 412 MSTPCR..................... 368, 390, 402, 412 P1DDR.......................... 88, 390, 402, 412 P1DR ............................ 88, 392, 403, 413 PADDR......................... 93, 390, 402, 412 PADR............................ 94, 392, 403, 413 PAODR......................... 95, 391, 402, 413 PAPCR.......................... 95, 391, 402, 412 PBDDR ......................... 97, 390, 402, 412 PBDR............................ 97, 392, 403, 413 PBODR ......................... 99, 391, 402, 413 PBPCR.......................... 98, 391, 402, 412 PCDDR ....................... 101, 390, 402, 412 PCDR.......................... 102, 392, 403, 413 PCODR ....................... 104, 391, 402, 413 PCPCR........................ 103, 391, 402, 412 PDDDR....................... 106, 390, 402, 412 PDDR.......................... 107, 392, 403, 413 PDPCR........................ 108, 391, 402, 412 PFDDR ....................... 108, 391, 402, 412 PFDR .......................... 109, 392, 403, 413 PORT1 .......................... 89, 394, 406, 415 PORT4 .......................... 92, 394, 406, 415 PORT9 .......................... 92, 394, 406, 415 PORTA ......................... 94, 394, 406, 415 PORTB ......................... 98, 394, 406, 415 PORTC ....................... 103, 394, 406, 415
PORTD ....................... 107, 394, 406, 415 PORTF ........................ 110, 394, 406, 415 RAMER ...................... 338, 392, 403, 413 RDR ............................ 206, 393, 405, 414 REC............................. 285, 382, 395, 407 RFPR........................... 279, 382, 395, 407 RSR .....................................................206 RSTCSR...................... 197, 393, 404, 414 RXPR .......................... 278, 382, 395, 407 SBYCR........................ 365, 390, 402, 412 SCKCR........................ 352, 390, 402, 412 SCMR ......................... 217, 393, 405, 414 SCR ............................. 210, 393, 405, 414 SMR ............................ 207, 393, 405, 414 SSR ............................. 212, 393, 405, 414 SYSCR .......................... 46, 390, 402, 412 TCNT .......................... 193, 393, 404, 414 TCR............................. 120, 392, 404, 414 TCSR........................... 193, 393, 404, 414 TDR............................. 206, 393, 405, 414 TEC ............................. 285, 382, 395, 407 TGR............................. 148, 392, 404, 414 TIER............................ 144, 392, 404, 414 TIOR ........................... 127, 392, 404, 414 TMDR ......................... 125, 392, 404, 414 TSR ............................. 145, 392, 404, 414 TSTR........................... 148, 392, 403, 413 TSYR .......................... 149, 392, 403, 413 TXACK....................... 276, 382, 395, 407 TXCR.......................... 275, 382, 395, 407 TXPR .......................... 274, 382, 395, 407 UMSR ......................... 286, 382, 395, 407 Reset..........................................................53 ROM .......................................................329 Boot Mode ..........................................340 Emulation ............................................343 Erase/Erase-Verify ..............................347 Erasing units........................................334 Program/Program-Verify ....................345 Programming units ..............................334 Programming/Erasing in User Program Mode ...................................................342
Rev. 0.5, 03/03, page 437 of 438
Serial Communication Interface (SCI) ... 203 Asynchronous Mode ........................... 225 Bit rate ................................................ 218 Break................................................... 263 Framing error ...................................... 232 Mark State........................................... 263 Overrun error ...................................... 232 Parity error .......................................... 232 Stack pointer (SP) ..................................... 18
Time Quanta (TQ)................................... 297 Trace Bit ................................................... 19 TRAPA instruction ................................... 57 Watchdog Timer Interval Timer Mode ........................... 200 Overflows............................................ 198 Watchdog Timer (WDT)......................... 191
Rev. 0.5, 03/03, page 438 of 438
H8S/2615 Series Hardware Manual Preliminary
Publication Date: 0.5th Edition, March 2003 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 2003. All rights reserved. Printed in Japan.

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